SEMICONDUCTOR DEVICE

• US 20150295092A1
• Filed: 09/19/2013
• Published: 10/15/2015
• Est. Priority Date: 10/01/2012
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Misaki, Katsunori
• Application Number:
  US14/432,540
• Publication Number:
  US 20150295092A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

This semiconductor device (201) includes a thin-film transistor (101) having an oxide semiconductor layer (5), wherein each of a source electrode (7) and a drain electrode (9) of the thin-film transistor (101) includes: a main layer (7a, 9a) containing a first metal; a lower layer (7c, 9c) arranged on the substrate side of the main layer, the lower layer (7c, 9c) including, in this order away from the main layer, a lower metal nitride layer made of a nitride of a second metal and a lower metal layer made of the second metal; and an upper layer (7b, 9b) arranged on the opposite side of the main layer from the substrate, the upper layer (7b, 9b) including, in this order away from the main layer, an upper metal nitride layer made of a nitride of the second metal and an upper metal layer made of the second metal, and wherein the first metal is aluminum or copper and the second metal is titanium or molybdenum.

Claims

1. :

A semiconductor device comprising a substrate, and a thin-film transistor supported on the substrate, wherein;

the thin-film transistor includes an oxide semiconductor layer, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer;

each of the source electrode and the drain electrode includes;

a main layer including a first metal;

a lower layer arranged on the substrate side of the main layer, the lower layer including, in this order away from the main layer, a lower metal nitride layer made of a nitride of a second metal and a lower metal layer made of the second metal; and

an upper layer arranged on the opposite side of the main layer from the substrate, the upper layer including, in this order away from the main layer, an upper metal nitride layer made of a nitride of the second metal and an upper metal layer made of the second metal; and

the first metal is aluminum or copper, and the second metal is titanium or molybdenum.

2. :

The semiconductor device of claim 1, wherein the lower metal nitride layer is in contact with a lower surface of the main layer, and the upper metal nitride layer is in contact with an upper surface of the main layer.

3. :

The semiconductor device of claim 1, wherein one of the lower metal layer and the upper metal layer is in contact with the oxide semiconductor layer.

4. :

The semiconductor device of claim 1, wherein the upper layer or the lower layer of the source electrode and the drain electrode further includes another metal nitride layer made of a nitride of the second metal and arranged so as to be in contact with the oxide semiconductor layer.

5. :

The semiconductor device of claim 1, further comprising a first protective layer covering the thin-film transistor, the first protective layer being a silicon oxide film, wherein;

the upper layer of the source electrode and the drain electrode further includes another metal nitride layer made of a nitride of the second metal and arranged between the upper metal layer and the first protective layer; and

the other metal nitride layer is in contact with the first protective layer.

6. :

The semiconductor device of claim 1, further comprising a first protective layer covering the thin-film transistor, the first protective layer being a silicon oxide film, wherein;

the gate electrode is arranged between the substrate and the oxide semiconductor layer;

the lower layer of the source electrode and the drain electrode further includes a lower metal nitride surface layer made of a nitride of the second metal and arranged between the lower metal layer and the oxide semiconductor layer;

the upper layer of the source electrode and the drain electrode further includes an upper metal nitride surface layer made of a nitride of the second metal and arranged between the upper metal layer and the first protective layer; and

the lower metal nitride surface layer is in contact with the oxide semiconductor layer, and the upper metal nitride surface layer is in contact with the first protective layer.

7. :

The semiconductor device of claim 1, further comprising an etch stop layer covering a channel region of the oxide semiconductor layer.

8. :

The semiconductor device of claim 1, wherein the oxide semiconductor layer is a layer containing an In—

Ga—

Zn—

O based oxide.

9. :

The semiconductor device of claim 8, wherein the oxide semiconductor layer is a layer containing a crystalline In—

Ga—

Zn—

O based oxide.