CONTINUOUS-TIME LINEAR EQUALIZER FOR HIGH-SPEED RECEIVING UNIT
First Claim
1. A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal, comprising:
- a signal line configured to provide an equalized output voltage; and
an active peaking control unit, comprising;
a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail;
a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and
a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.
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Accused Products
Abstract
A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.
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Citations
21 Claims
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1. A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal, comprising:
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a signal line configured to provide an equalized output voltage; and an active peaking control unit, comprising; a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification