SELF-AUTHENTICATING CHIPS
First Claim
1. A self-authenticating chip comprising:
- a first memory region storing a first authentication code;
a second memory region storing a second authentication code, said second memory region adapted to be unreadable and unmodifiable by said chip or a chip reader;
a comparator interconnected to said second memory region for providing an indicator of whether given input matches said second authentication code; and
an authentication circuit interconnected to said comparator and said first memory region;
said authentication circuit operable to;
read said first authentication code from said first memory region;
present said first authentication code to said comparator; and
in response to receiving an indicator from said comparator indicating that said first authentication code matches said second authentication code;
unlock at least one of (i) a communication interface of said chip to allow data to be transmitted therethrough to a chip reader and (ii) a third memory region of said chip to allow data to be read therefrom.
2 Assignments
0 Petitions
Accused Products
Abstract
A self-authenticating chip includes first and second memory regions storing, respectively, first and second authentication codes. The second memory region is adapted to be unreadable and unmodifiable by the chip or a chip reader. The chip also includes a comparator for providing an indicator of whether given input matches the second authentication code. The chip also includes an authentication circuit that is operable to read the first authentication code from the first memory region, present the first authentication code to the comparator, and in response to receiving an indicator from the comparator indicating that the first and second authentication codes match, unlock at least one of (i) a communication interface of the chip to allow data to be transmitted therethrough to a chip reader and (ii) a third memory region of the chip to allow data to be read therefrom.
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Citations
35 Claims
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1. A self-authenticating chip comprising:
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a first memory region storing a first authentication code; a second memory region storing a second authentication code, said second memory region adapted to be unreadable and unmodifiable by said chip or a chip reader; a comparator interconnected to said second memory region for providing an indicator of whether given input matches said second authentication code; and an authentication circuit interconnected to said comparator and said first memory region; said authentication circuit operable to; read said first authentication code from said first memory region; present said first authentication code to said comparator; and in response to receiving an indicator from said comparator indicating that said first authentication code matches said second authentication code; unlock at least one of (i) a communication interface of said chip to allow data to be transmitted therethrough to a chip reader and (ii) a third memory region of said chip to allow data to be read therefrom. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 32, 33, 34, 35)
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23. A self-authenticating card comprising:
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a first chip having a first memory region storing a first authentication code, and a communication interface for communicating with a chip reader; and a second chip having a second memory region storing a second authentication code; at least one of said first and second chips providing an authentication circuit interconnected with said first memory region and said second memory region, said authentication circuit operable to; read said first authentication code from said first memory region; read said second authentication code from said second memory region; authenticate said card by comparing said first authentication code with said second authentication code; and upon said authenticating; unlock at least one of (i) said communication interface to allow data to be transmitted therethrough (ii) a third memory region to allow data to be read therefrom. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
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Specification