SCHEDULING OF SCENARIO MODELS FOR EXECUTION WITHIN DIFFERENT COMPUTER THREADS AND SCHEDULING OF MEMORY REGIONS FOR USE WITH THE SCENARIO MODELS

• US 20150301108A1
• Filed: 04/17/2015
• Published: 10/22/2015
• Est. Priority Date: 04/18/2014
• Status: Active Grant

• Current Assignee: Breker Verification Systems, Inc.
• Original Assignee: Breker Verification Systems, Inc.
• Inventors: Hamid, Adnan, Qian, Kairong, Do, Kieu
• Granted Patent: US 9,316,689 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/3688 for test execution, e.g. scheduling of test suites
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 3/0484 for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06T 11/206 Drawing of charts or graphs

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Claims

1. A method comprising:

receiving multiple application scenario models, the application scenario models generated for testing one or more systems on chips (SoCs), wherein the application scenario models include a plurality of driver scenario models, wherein the application scenario models include a plurality of sequences of execution of the driver scenario models, wherein each application scenario model is generated by backpropagating an expected output of the application scenario model to generate an input to be provided to the application scenario model during a test of the one or more SoCs;

splitting the application scenario models into a pre-determined number of computer threads, each computer thread including at least one but not all of the driver scenario models;

splitting the sequences into a plurality of flows between the driver scenario models of the computer threads; and

providing for testing of the one or more SoCs the driver scenario models within the computer threads and the plurality of flows between the driver scenario models of the computer threads.

2. The method of claim 1, wherein providing for testing comprises providing for simultaneous execution within one of the computer threads one of the driver scenario models of one of the application scenario models and within another one of the computer threads another one of the driver scenario models of another one of the application scenario models.

3. The method of claim 1, wherein the computer threads are executed on multiple processors.

4. The method of claim 1, wherein the computer threads are executed on a processor.

5. The method of claim 1, wherein the application scenario models include links between the driver scenario models, each link providing a direction of flow between corresponding two of the driver scenario models.

6. The method of claim 1, wherein each driver scenario model is a function.

7. The method of claim 1, wherein each sequence of execution is a sequence of execution of two or more of the driver scenario models of one of the application scenario models.

8. The method of claim 1, wherein the plurality of flows between the driver scenario models includes a flow between one of the driver scenario models in one of the computer threads and another one of the driver scenario models in another one of the computer threads.

9. The method of claim 1, wherein providing for testing comprises:

providing for execution a first one of the driver scenario models in one of the computer threads, one of the flows indicating execution of a second one of the driver scenario models after the execution of the first driver scenario model; and

providing for execution the second driver scenario model in another one of the computer threads upon execution of the first driver scenario model according to the flow to generate a test result.

10. The method of claim 9, further comprising comparing the test result with an expected outcome to determine whether the one or more SoCs passes a test.

11. A method comprising:

receiving multiple application scenario models, wherein the application scenario models include a plurality of driver scenario models and sequences of application of the driver scenario models, wherein the application scenario models are used for testing one or more systems on chips (SoCs), wherein each application scenario model is generated by backpropagating an expected output of the application scenario model to generate an input to be provided to the application scenario model during a test of the one or more SoCs; and

splitting multiple memory addresses into a plurality of memory regions, each of the memory regions exclusive of any other of the memory regions,

wherein one of the driver scenario models of one of the application scenario models includes reading data from one of the memory regions,

wherein another one of the driver scenario models of the one of the application scenario model includes writing data to another one of the memory regions.

12. The method of claim 11, further comprising generating a test file for testing a design of the one or more SoCs, wherein the design is tested by performing the reading of data from the one of the memory regions and by performing the writing of data to the other one of the memory regions.

13. The method of claim 11, wherein the one of the driver scenario models of the one of the application scenario models reads data from the one of the memory regions simultaneously with a read operation performed by another one of the driver scenario models of another one of the application scenario models.

14. The method of claim 11, wherein one of the memory regions is a memory address in a memory device and another one of the memory regions is a memory address in the same memory device or another memory device.

15. A system comprising:

a memory device for storing application scenario models, wherein the application scenario models are generated for testing one or more systems on chips (SoCs), wherein the application scenario models include a plurality of driver scenario models, wherein the application scenario models include a plurality of sequences of execution of the driver scenario models, wherein each application scenario model is generated by backpropagating an expected output of the application scenario model to generate an input to be provided to the application scenario model during a test of the one or more SoCs; and

a processor coupled to the memory device, the processor for;

receiving the application scenario models;

splitting the application scenario models into a pre-determined number of computer threads, each computer thread including at least one but not all of the driver scenario models;

splitting the sequences into a plurality of flows between the driver scenario models of the computer threads; and

providing for testing of the one or more SOCs the driver scenario models within the computer threads and the plurality of flows between the driver scenario models of the computer threads.

16. The system of claim 15, the processor is configured to execute within one of the computer threads one of the driver scenario models of one of the application scenario models and within another one of the computer threads another one of the driver scenario models of another one of the application scenario models.

17. The system of claim 15, wherein the computer threads are configured for execution on multiple processors.

18. The system of claim 15, wherein the computer threads are executed on a single processor.

19. The system of claim 15, wherein the application scenario models include links between the driver scenario models and a direction of flow between the driver scenario models.

20. The system of claim 15, wherein each driver scenario model is a function.