Dynamic Temporary Use of Packet Memory As Resource Memory

• US 20150301963A1
• Filed: 04/21/2014
• Published: 10/22/2015
• Est. Priority Date: 04/21/2014
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Tatar, Mohammed Ismael, Carney, John C., Nedungadi, Promode, Hasani, Naader
• Granted Patent: US 9,846,658 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: H04L 49/9005 using dynamic buffer space allocation

Abstract

In one embodiment, packet memory and resource memory of a memory are independently managed, with regions of packet memory being freed of packets and temporarily made available to resource memory. In one embodiment, packet memory regions are dynamically made available to resource memory so that in-service system upgrade (ISSU) of a packet switching device can be performed without having to statically allocate (as per prior systems) twice the memory space required by resource memory during normal packet processing operations. One embodiment dynamically collects fragments of packet memory stored in packet memory to form a contiguous region of memory that can be used by resource memory in a memory system that is shared between many clients in a routing complex. One embodiment assigns a contiguous region no longer used by packet memory to resource memory, and from resource memory to packet memory, dynamically without packet loss or pause.

Claims

1. A method, comprising:

buffering packets in packet memory of memory of a packet switching device, with said memory including resource memory, with said packet memory and said resource memory being independently managed, and with said packet memory including a plurality of packet memory regions of memory;

using forwarding information stored in the resource memory to forward packets of said buffered packets; and

in response to a condition and while said buffering packets and said using forwarding information stored in the resource memory to forward said buffered packets;

acquiring one or more regions from the plurality of packet memory regions by a memory controller, assigning said acquired packet memory regions to be part of said resource memory, performing additional operations using said resource memory including said acquired packet memory, and subsequent to said performing additional operations, acquiring a portion of the resource memory by the memory controller and assigning said acquired portion of the resource memory to said packet memory with said buffering packets including buffering packets in said packet memory including said assigned acquired portion of the resource memory.

2. The method of claim 1, wherein said additional operations include in-service system upgrade of the packet switching device.

3. The method of claim 2, wherein said assigning said acquired packet memory regions to be part of said resource memory at least doubles the used prior amount of said resource memory.

4. The method of claim 2, wherein said in-service system upgrade of the packet switching device is performed with zero packet loss.

5. The method of claim 4, wherein said packet memory including the plurality of packet memory regions of memory is sized to accommodate peak burst rate packet traffic;

and wherein said packet memory without said acquired packet memory regions cannot accommodate said peak burst rate packet traffic.

6. The method of claim 5, wherein said acquiring one or more regions from the plurality of packet memory regions by a memory controller includes adjusting the packet distribution of said buffering packets in packet memory to stop buffering packets in a portion of said packet memory including said one or more regions of the plurality of packet memory regions such that by attrition of removing one or more packets there are no packets stored in said one or more regions of the plurality of packet memory regions.

7. The method of claim 1, wherein said packet memory including the plurality of packet memory regions of memory is sized to accommodate peak burst rate packet traffic;

and wherein said packet memory without said acquired packet memory regions cannot accommodate said peak burst rate packet traffic.

8. The method of claim 1, wherein said acquiring one or more regions from the plurality of packet memory regions by a memory controller includes adjusting the packet distribution of said buffering packets in packet memory to stop buffering packets in a portion of said packet memory including said one or more regions of the plurality of packet memory regions such that by attrition of removing one or more packets there are no packets stored in said one or more regions of the plurality of packet memory regions.

9. The method of claim 1, wherein said acquiring one or more regions from the plurality of packet memory regions by a memory controller includes adjusting the packet distribution of said buffering packets in packet memory to stop buffering packets in a portion of said packet memory including said one or more regions of the plurality of packet memory regions, and after a subsequent predetermined time moving one or more remaining packets such that there are no packets stored in said one or more regions of the plurality of packet memory regions.

10. The method of claim 1, wherein said memory is located on a line card of the packet switching device.

11. The method of claim 1, wherein one or more regions from the plurality of packet memory regions consists of a single region.

12. The method of claim 1, wherein said acquiring one or more regions from the plurality of packet memory regions by a memory controller includes concentrating packets of said buffering packets in regions other than one or more regions of the plurality of packet memory regions.

13. The method of claim 1, wherein said acquiring one or more regions from the plurality of packet memory regions by a memory controller includes designating said one or more regions of the plurality of packet memory regions.

14. The method of claim 1, wherein said acquiring one or more regions from the plurality of packet memory regions by a memory controller includes designating said one or more regions of the plurality of packet memory regions based on an age or utilization metric of said one or more regions.

15. The method of claim 1, wherein said buffering packets sparsely populates each region currently assigned to said packet memory.

16. The method of claim 1, wherein said memory is located on a single memory system application-specific integrated circuit (ASIC).

17. A packet switching device, comprising:

a packet switching mechanism configured to packet switch packets within the packet switching device;

a route processor, including at least one processing element, communicatively coupled to the packet switching mechanism; and

a plurality of line cards, with each line card of the plurality of line cards communicatively coupled to the packet switching mechanism and including;

memory comprising independently managed packet memory and resource memory, with said packet memory configured to buffer packets and including a plurality of packet memory regions of memory with a total size to accommodate peak burst rate packet traffic; and

one or more packet processors configured to use forwarding information stored in the resource memory to forward packets of said buffered packets; and

a memory manager configured to perform operations without causing packet loss including to acquire one or more regions from the plurality of packet memory regions, assign said acquired packet memory regions to be part of said resource memory, and to return said acquired packet memory regions to the plurality of packet memory regions.

18. The packet switching device of claim 17, wherein said configuration to return said acquired packet memory regions to the plurality of packet memory regions is responsive to an in-service system upgrade of the packet switching device using said resource memory which could not be performed with the size of resource memory prior to said assignment of said acquired packet memory regions to be part of said resource memory.

19. A method, comprising:

buffering packets in packet memory of memory on a single integrated circuit of a packet switching device, with said memory including resource memory, with said packet memory and said resource memory being independently managed, and with said packet memory including a plurality of packet memory regions of memory and sized to accommodate peak burst rate packet traffic, with said buffering packets including distributing packets throughout currently assigned regions to said packet memory;

using forwarding infoiination stored in the resource memory to forward packets of said buffered packets; and

while said buffering packets and said using forwarding information stored in the resource memory to forward said buffered packets;

acquiring one or more regions from the plurality of packet memory regions by a memory controller, assigning said acquired packet memory regions to be part of said resource memory, and performing additional operations using said resource memory including said acquired packet memory.

20. The method of claim 19, wherein said additional operations include in-service system upgrade of the packet switching device which could not be perfonued with the size of resource memory prior to said assignment of said acquired packet memory regions to be part of said resource memory.