SEMICONDUCTOR MEMORY DEVICE
First Claim
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1. A semiconductor memory device, comprising:
- a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and
a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals,wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.
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Abstract
A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.
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Citations
13 Claims
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1. A semiconductor memory device, comprising:
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a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory device, comprising:
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a plurality of stacked memory chips each suitable for reading data from a plurality of memory cells included therein in response to a read command and outputting the read data in response to a corresponding control signal of a plurality of first control signals, wherein a first memory chip among the memory chips includes; a control signal generation block suitable for generating the first control signals and a second control signal based on the read command; and a first pipe latch block suitable for latching the data outputted from the memory chips based on the first control signals and outputting the latched data to a data pad based on the second control signal. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification