SEMICONDUCTOR MEMORY DEVICE

• US 20150302915A1
• Filed: 11/06/2014
• Published: 10/22/2015
• Est. Priority Date: 04/22/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: PARK, Min-Su, KU, Young-Jun
• Granted Patent: US 9,336,857 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

Claims

1. A semiconductor memory device, comprising:

a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and

a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals,

wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

2. The semiconductor memory device of claim 1, wherein the master chip includes:

a control signal generation block suitable for generating the first control signals and the second control signal based on the read command;

a signal combination block suitable for combining the first control signals and outputting a combination signal; and

a first pipe latch block suitable for latching the data transmitted from the slave chips based on the combination signal and outputting the data latched in the first pipe latch based on the second control signal.

3. The semiconductor memory device of claim 2, wherein each of the slave chips includes:

a second pipe latch block suitable for latching the data read from the memory cells included in a corresponding slave chip and outputting the data latched in the second pipe latch based on a corresponding first control signal.

4. The semiconductor memory device of claim 3, wherein the first pipe latch block of the master chip and the second pipe latch block of each of the slave chips include a plurality of latch circuits, and the number of the latch circuits included in the second pipe latch block are in inverse proportion to the number of the latch circuits included in the first pipe latch block.

5. The semiconductor memory device of claim 2, wherein the control signal generation block generates the first and second control signals according to column address strobe latency.

6. The semiconductor memory device of claim 1, wherein the slave chips are stacked in an upper portion of the master chip.

7. The semiconductor memory device of claim 6, wherein the slave chips have a through-silicon via through which the data is transmitted to the master chip.

8. A semiconductor memory device, comprising:

a plurality of stacked memory chips each suitable for reading data from a plurality of memory cells included therein in response to a read command and outputting the read data in response to a corresponding control signal of a plurality of first control signals,

wherein a first memory chip among the memory chips includes;

a control signal generation block suitable for generating the first control signals and a second control signal based on the read command; and

a first pipe latch block suitable for latching the data outputted from the memory chips based on the first control signals and outputting the latched data to a data pad based on the second control signal.

9. The semiconductor memory device of claim 8, wherein the first memory chip further includes:

a signal combination block suitable for combining the first control signals and transmitting the combined signals to the first pipe latch block.

10. The semiconductor memory device of claim 8, wherein each of the memory chips includes:

a second pipe latch block suitable for latching the read data and outputting the data latched in the second pipe latch block based on a corresponding first control signal.

11. The semiconductor memory device of claim 10, wherein the first and second pipe latch blocks include a plurality of latch circuits, and the number of the latch circuits included in the second pipe latch block are in inverse proportion to the number of the latch circuits included in the first pipe latch block.

12. The semiconductor memory device of claim 8, wherein the control signal generation block generates the first and second control signals according to column address strobe latency.

13. The semiconductor memory device of claim 8, wherein the memory chips have a through-silicon via through which the data is transmitted.