THREE-DIMENSIONAL (3D) MEMORY CELL SEPARATION AMONG 3D INTEGRATED CIRCUIT (IC) TIERS, AND RELATED 3D INTEGRATED CIRCUITS (3DICs), 3DIC PROCESSOR CORES, AND METHODS

• US 20150302919A1
• Filed: 07/02/2015
• Published: 10/22/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Xie, Jing, Du, Yang
• Granted Patent: US 9,583,179 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Claims

1. A three-dimensional (3D) memory block, comprising:

a memory cell disposed in a first tier of a 3D integrated circuit (IC) (3DIC);

at least one read access port disposed in a second tier of the 3DIC, the at least one read access port configured to provide read access to the memory cell, wherein each read access port of the at least one read access port comprises a read transistor coupled to the memory cell; and

at least one monolithic intertier via (MIV) coupling the at least one read access port to the memory cell.

2. The 3D memory block of claim 1, further comprising at least one write access port disposed in the first tier of the 3DIC, the at least one write access port configured to provide write access to the memory cell.

3. The 3D memory block of claim 1, further comprising at least one write access port disposed in the second tier of the 3DIC, the at least one write access port configured to provide write access to the memory cell through the at least one MIV.

4. The 3D memory block of claim 1, further comprising:

a processor core write logic disposed in the first tier of the 3DIC, the processor core write logic configured to provide write requests to at least one write access port of the memory cell; and

a processor core read logic disposed in the second tier of the 3DIC, the processor core read logic configured to provide read accesses to the at least one read access port of the memory cell.

5. The 3D memory block of claim 1, further comprising:

a first voltage rail supplied with a first voltage disposed in the first tier of the 3DIC, the first voltage rail configured to supply the first voltage to the memory cell; and

a second voltage rail supplied with a second voltage lower than the first voltage supplied to the first voltage rail, the second voltage rail disposed in the second tier of the 3DIC and configured to supply the second voltage to the at least one read access port.

6. The 3D memory block of claim 1 integrated into a semiconductor die.

7. The 3D memory block of claim 1, further comprising a device selected from the group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player, into which the 3D memory block is integrated.

8. The 3D memory block of claim 1, wherein the 3D memory block comprises a register within an integrated circuit.

9. The 3D memory block of claim 1, wherein the 3D memory block comprises cache memory within an integrated circuit.

10. A three-dimensional (3D) memory block, comprising:

a memory cell disposed in a first tier of a 3D integrated circuit (IC) (3DIC);

a first voltage rail supplied with a first voltage disposed in the first tier of the 3DIC, the first voltage rail configured to supply the first voltage to the memory cell;

at least one read access port disposed in a second tier of the 3DIC, the at least one read access port configured to provide read access to the memory cell;

a second voltage rail supplied with a second voltage lower than the first voltage supplied to the first voltage rail, the second voltage rail disposed in the second tier of the 3DIC and configured to supply the second voltage to the at least one read access port; and

at least one monolithic intertier via (MIV) coupling the at least one read access port to the memory cell.

11. The 3D memory block of claim 10, further comprising at least one write access port disposed in the first tier of the 3DIC, the at least one write access port configured to provide write access to the memory cell.

12. The 3D memory block of claim 10, further comprising at least one write access port disposed in the second tier of the 3DIC, the at least one write access port configured to provide write access to the memory cell through the at least one MIV.

13. The 3D memory block of claim 10, further comprising:

a processor core write logic disposed in the first tier of the 3DIC, the processor core write logic configured to provide write requests to at least one write access port of the memory cell; and

a processor core read logic disposed in the second tier of the 3DIC, the processor core read logic configured to provide read accesses to the at least one read access port of the memory cell.

14. The 3D memory block of claim 10, wherein the memory cell comprises a static random access memory (SRAM) element.

15. A method of forming a three-dimensional (3D) memory block, comprising:

forming a first tier of a 3D integrated circuit (IC) (3DIC);

forming a memory cell within the first tier of the 3DIC;

forming a second tier of the 3DIC;

forming at least one read access port within the second tier of the 3DIC, the at least one read access port configured to provide read access to the memory cell, wherein forming the at least one read access port comprises forming a read transistor coupled to the memory cell; and

coupling the at least one read access port to the memory cell with at least one monolithic intertier via (MIV).

16. The method of claim 15, further comprising forming at least one write access port within the first tier of the 3DIC, the at least one write access port configured to provide write access to the memory cell.

17. The method of claim 15, further comprising forming at least one write access port within the second tier of the 3DIC, the at least one write access port configured to provide write access to the memory cell through the at least one MIV.

18. The method of claim 15, further comprising configuring the memory cell to operate as a register.

19. The method of claim 15, further comprising:

forming a processor core write logic within the first tier of the 3DIC, the processor core write logic configured to provide write requests to at least one write access port of the memory cell; and

forming a processor core read logic within the second tier of the 3DIC, the processor core read logic configured to provide read accesses to the at least one read access port of the memory cell.

20. The method of claim 15, further comprising:

forming a first voltage rail within the first tier of the 3DIC, the first voltage rail configured to supply a first voltage to the memory cell; and

forming a second voltage rail within the second tier of the 3DIC, the second voltage rail configured to supply a second voltage to the at least one read access port.