MULTILAYER CERAMIC CAPACITOR AND CIRCUIT BOARD FOR MOUNTING THE SAME

• US 20150302991A1
• Filed: 07/23/2014
• Published: 10/22/2015
• Est. Priority Date: 04/16/2014
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: CHOI, Woo Jin
• Granted Patent: US 9,524,827 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01G 2/065 for surface mounting, e.g. chip capacitors
• CPC Class Codes: H01G 4/12 Ceramic dielectrics H01G4/085 takes precedence
• CPC Class Codes: H01G 4/1227 based on alkaline earth titanates
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H05K 1/182 associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
• CPC Class Codes: H05K 1/183 Components mounted in and supported by recessed areas of the printed circuit board

Abstract

A multilayer ceramic capacitor may include: a ceramic body in which dielectric layers having first via holes are stacked in a thickness direction; first internal electrodes having second via holes disposed in positions corresponding to those of the first via holes and exposed to at least one side surface of the ceramic body; second internal electrodes having third via holes disposed in positions corresponding to those of the first and second via holes; a via electrode passing through the first to third via holes to thereby be exposed to upper and lower surfaces of the ceramic body, and connected to the third via holes; and a first external electrode disposed on the at least one side surface of the ceramic body to be connected to a portion of the first internal electrode exposed to the exterior of the ceramic body.

Claims

1. A multilayer ceramic capacitor, comprising:

a ceramic body in which dielectric layers having first via holes are stacked in a thickness direction;

first internal electrodes having second via holes disposed in positions corresponding to those of the first via holes and exposed to at least one side surface of the ceramic body;

second internal electrodes having third via holes disposed in positions corresponding to those of the first and second via holes;

a via electrode passing through the first to third via holes to thereby be exposed to upper and lower surfaces of the ceramic body, and connected to the third via holes; and

a first external electrode disposed on the at least one side surface of the ceramic body to be connected to a portion of the first internal electrode exposed to an exterior of the ceramic body.

2. The multilayer ceramic capacitor of claim 1, wherein an area of a surface of the first internal electrode is equal to that of a surface of the dielectric layer.

3. The multilayer ceramic capacitor of claim 1, wherein a diameter of the second via hole is larger than those of the first and third via holes.

4. The multilayer ceramic capacitor of claim 3, wherein a dielectric part is disposed between an inner surface of the second via hole and an outer surface of the via electrode.

5. The multilayer ceramic capacitor of claim 1, further comprising a second external electrode disposed on at least one of the upper and lower surfaces of the ceramic body and connected to the via electrode.

6. The multilayer ceramic capacitor of claim 1, wherein the first internal electrode is exposed to two side surfaces of the ceramic body opposing each other among side surfaces of the ceramic body, and

the first external electrode is disposed on the two side surfaces of the ceramic body to which the first internal electrode is exposed among the side surfaces of the ceramic body to thereby be connected to the first internal electrode.

7. The multilayer ceramic capacitor of claim 1, wherein the first external electrode is disposed on all side surfaces of the ceramic body except for the upper and lower surfaces of the ceramic body.

8. The multilayer ceramic capacitor of claim 1, wherein the first external electrode is extended to portions of the upper and lower surfaces of the ceramic body.

9. The multilayer ceramic capacitor of claim 1, wherein the number of via electrodes is two or greater.

10. A circuit board having a multilayer ceramic capacitor, wherein the multilayer ceramic capacitor includes:

a ceramic body in which dielectric layers having first via holes are stacked in a thickness direction;

first internal electrodes having second via holes disposed in positions corresponding to those of the first via holes and exposed to at least one side surface of the ceramic body;

second internal electrodes having third via holes disposed in positions corresponding to those of the first and second via holes;

a via electrode disposed in the first to third via holes and passing through the first to third via holes to thereby be exposed to upper and lower surfaces of the ceramic body; and

a first external electrode disposed on the at least one side surface of the ceramic body and connected to a portion of the first internal electrode exposed to the exterior of the ceramic body.