Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

• US 20150303174A1
• Filed: 07/09/2014
• Published: 10/22/2015
• Est. Priority Date: 04/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Yee, Kuo-Chung
• Granted Patent: US 9,601,463 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/92225 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1438 : Flash memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

Claims

1. A package comprising:

a first fan-out tier comprising;

a first device die;

a first molding compound extending along sidewalls of the first device die; and

a first through intervia (TIV) extending through the first molding compound;

one or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;

a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;

one or more second fan-out RDLs on an opposing side of the first fan-out tier as the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; and

a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

2. The package of claim 1, wherein the second fan-out tier further comprises:

a second molding compound extending along sidewalls of the second device die; and

a second TIV extending through the second molding compound.

3. The package of claim 2, wherein the second fan-out tier further comprises a third device die bonded to one or more first fan-out RDLs, wherein the second TIV is disposed between the second and the third device dies.

4. The package of claim 2, wherein the second fan-out tier further comprises a fourth device die, wherein back surfaces of the second device die and the fourth device die are bonded by an adhesive layer.

5. The package of claim 1, further comprising one or more third fan-out RDLs between the one or more first fan-out RDLs and the second fan-out tier, wherein the second device die is bonded to the one or more third fan-out RDLs, and wherein a plurality of connectors bonds the one or more third fan-out RDLs to the one or more second fan-out RDLs.

6. The package of claim 1 further comprising:

one or more third fan-out RDLs over the second fan-out tier, wherein the one or more third fan-out RDLs is electrically connected to the one or more second fan-out RDLs; and

a third fan-out tier disposed over the one or more third fan-out RDLs, the third fan-out tier comprising a fifth device die bonded to the one or more third fan-out RDLs, and wherein the one or more third fan-out RDLs electrically connects the fifth device die to the first device die.

7. The package of claim 1 further comprising one or more heat dissipation features on a surface of the package.

8. A package comprising:

a first device die;

a first fan-out tier bonded to the first device die, the first fan-out tier comprising;

a second device die;

a first molding compound extending along sidewalls of the second device die; and

a first through intervia (TIV) extending through the first molding compound;

a first fan-out RDL bonded to the first fan-out tier; and

a third device die electrically connected to the first fan-out RDL, wherein the first device die is electrically connected to the third device die by a first dedicated signaling path comprising the first TIV.

9. The package of claim 8, wherein the first device die and the second device die are electrically isolated from each other.

10. The package of claim 8, the second device die comprises a through-silicon via (TSV), wherein the TSV electrically connects the first and the second device dies.

11. The package of claim 8, wherein the third device die is disposed in a second fan-out tier, the second fan-out tier further comprising:

a second molding compound extending along sidewalls of the third device die; and

a second TIV extending through the second molding compound, wherein the first dedicated signaling path comprises the second TIV.

12. The package of claim 8, wherein the second device die is electrically connected to the third device die by a second dedicated signaling path, the second dedicated signaling path being electrically isolated from the first dedicated signaling path.

13. The package of claim 8, wherein the first device die is disposed in a second fan-out tier, and wherein the first device die is bonded to a second fan-out RDL disposed between the first and the second fan-out tiers.

14. The package of claim 8, wherein the first dedicated signaling path electrically connects the first device die to an external connector disposed on a surface of the package.

15. A method for forming a package comprising:

forming one or more first fan-out redistribution layers (RDLs) comprising a conductive line;

forming a fan-out tier over the one or more first fan-out RDLs, wherein forming the fan-out tier comprises;

forming a first through intervia (TIV) over the one or more first fan-out RDLs;

bonding a first device die to the one or more first fan-out RDLs;

dispensing a first molding compound around the first device die and the first TIV; and

exposing connectors on the first device die and the first TIV;

forming one or more second fan-out RDLs over the fan-out tier, wherein the first TIV electrically connects the one or more second fan-out RDLs to the one or more first fan-out RDLs;

bonding a second device die to the one or more second fan-out RDLs, wherein the one or more second fan-out RDLs electrically connects the first and the second device dies;

patterning the one or more first fan-out RDLs to expose the conductive line; and

disposing an external connector on the conductive line, wherein the external connector is at least partially disposed in the one or more first fan-out RDLs.

16. The method of claim 15, wherein patterning the one or more first fan-out RDLs to expose the conductive line comprises laser drilling.

17. The method of claim 15, wherein bonding the first device die comprises adhering the first device die to the one or more first fan-out RDLs using an adhesive layer on a backside of the first device die.

18. The method of claim 15, further comprising:

forming a second TIV over the one or more second fan-out RDLs;

dispensing a second molding compound around the second device die and the second TIV;

exposing the second TIV;

forming one or more third fan-out RDLs over the second TIV and the second device die, wherein the second TIV electrically connects the one or more third fan-out RDLs to the one or more second fan-out RDLs; and

bonding a third device die to the one or more third fan-out RDLs, wherein the one or more third fan-out RDLs electrically connects the first and the third device dies.

19. The method of claim 15 wherein forming the first TIV comprises:

disposing a photoresist over the one or more first fan-out RDLs;

patterning an opening in the photoresist;

filling the opening with a conductive material; and

removing the photoresist.

20. The method of claim 19, wherein forming the first TIV further comprises disposing seed layer between the photoresist and the one or more fan-out RDLs, wherein the opening exposes the seed layer, and wherein filling the opening comprises using the seed layer in a uni-directional electroless or electrochemical plating process.