NONVOLATILE MEMORY DEVICE
First Claim
1. A nonvolatile memory device comprising:
- a first active region and a second active region separated from each other;
a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region;
a selection gate crossing the first active region, disposed side by side, and coupled to the floating gate;
a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure;
a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and
a contact commonly coupled to the well region and the selection gate.
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Accused Products
Abstract
A nonvolatile memory device includes a first active region and a second active region separated from each other; a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region; a selection gate crossing the first active region, and disposed side by side with and coupled to the floating gate; a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure; a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and a contact commonly coupled to the well region and the selection gate.
8 Citations
21 Claims
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1. A nonvolatile memory device comprising:
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a first active region and a second active region separated from each other; a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region; a selection gate crossing the first active region, disposed side by side, and coupled to the floating gate; a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure; a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and a contact commonly coupled to the well region and the selection gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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13. A nonvolatile memory device comprising:
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a charge storage transistor including a floating gate, a first junction region which is coupled to a source line, and a third junction region; a selection transistor including a selection gate which is coupled to a word line, a second junction region which is coupled to a bit line, and the third junction region which is shared by the charge storage transistor; a first capacitor component disposed between a terminal of the selection gate and a terminal of the floating gate; and a diode component and a second capacitor component disposed in series between the terminal of the selection gate and the terminal of the floating gate.
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14. The nonvolatile memory device according to claim 12,
wherein the first capacitor component and the second capacitor component are coupled to each other in parallel between the terminals of the selection gate and the floating gate.
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15. The nonvolatile memory device according to claim 12, further comprising:
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a dielectric layer disposed between the floating gate and the selection gate, wherein the first capacitor component includes the floating gate, the dielectric layer and the selection gate.
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16. The nonvolatile memory device according to claim 12,
wherein an anode and a cathode of the diode component are respectively coupled to the selection gate and the second capacitor component.
- 18. The nonvolatile memory device according to claim 12, wherein a bias voltage commonly applied to the word line is coupled to the floating gate by the first capacitor component and the second capacitor component in such a manner that coupling voltages are induced.
Specification