Vertical Semiconductor Device

• US 20150303260A1
• Filed: 04/06/2015
• Published: 10/22/2015
• Est. Priority Date: 04/16/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Pfaffenlehner, Manfred, Schulze, Hans-Joachim, Schulze, Holger, Umbach, Frank, Weiss, Christoph, Niedernostheide, Franz Josef
• Granted Patent: US 10,957,764 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor body includes first and second opposing surfaces, an edge extending in a vertical direction substantially perpendicular to the first surface, an active area, a peripheral area arranged in a horizontal direction substantially parallel to the first surface between the active area and edge, and a pn-junction extending from the active area into the peripheral area. In the peripheral area the semiconductor device further includes a first conductive region arranged next to the first surface, a second conductive region arranged next to the first surface, and arranged in the horizontal direction between the first conductive region and edge, and a passivation structure including a first portion at least partly covering the first conductive region, a second portion at least partly covering the second conductive region. The first portion has a different layer composition than the second portion and/or a thickness which differs from the thickness of the second portion.

Claims

1. A vertical semiconductor device, comprising:

a semiconductor body comprising a first surface, a second surface opposite the first surface, an edge extending in a vertical direction substantially perpendicular to the first surface, an active area, a peripheral area arranged in a horizontal direction substantially parallel to the first surface between the active area and the edge, and a pn-junction arranged next to the first surface and extending from the active area into the peripheral area,

wherein in the peripheral area the semiconductor device further comprises;

a first conductive region arranged next to the first surface;

a second conductive region arranged next to the first surface, and arranged in the horizontal direction between the first conductive region and the edge; and

a passivation structure comprising in a vertical cross-section a first portion at least partly covering the first conductive region, and a second portion at least partly covering the second conductive region, wherein the first portion comprises a first thickness which differs from a second thickness of the second portion and/or wherein the first portion comprises a different layer composition than the second portion.

2. The vertical semiconductor device of claim 1, wherein at least one of the first conductive region and the second conductive region is arranged on the first surface and formed as a field plate.

3. The vertical semiconductor device of claim 1, further comprising at least one of a dielectric layer arranged on the passivation structure and a further dielectric layer arranged between the semiconductor body and the first conductive region and/or the second conductive region.

4. The vertical semiconductor device of claim 1, wherein the second thickness is lower than the first thickness.

5. The vertical semiconductor device of claim 1, wherein the second thickness and the first thickness differ by at least 50%.

6. The vertical semiconductor device of claim 1, wherein the second thickness is lower than about 100 nm, and wherein the first thickness is in a range from about 200 nm to about 800 nm.

7. The vertical semiconductor device of claim 3, wherein the at least one dielectric layer comprises an organic material.

8. The vertical semiconductor device of claim 1, wherein the passivation structure comprises an oxide, a nitride, an oxynitride and/or a diamond-like carbon.

9. The vertical semiconductor device of claim 1, wherein the pn-junction extends in the peripheral area to the first surface.

10. The vertical semiconductor device of claim 1, further comprising at least one of:

a first metallization arranged on the first surface;

a second metallization arranged on the second surface such that the pn-junction forms a rectifying junction between the first metallization and the second metallization;

a third metallization on the first surface, in Ohmic contact with the third conductive region and isolated from the semiconductor body;

a channel-stopper region arranged next to the first surface and the edge, adjoining the first semiconductor region and having a higher doping concentration than the first semiconductor region;

a dielectric layer arranged on the passivation structure; and

a sealing layer arranged on the dielectric layer.

11. The vertical semiconductor device of claim 1, wherein the active area comprises a plurality of IGBT-cells, MOSFET-cells and/or diode-cells.

12. A vertical semiconductor device, comprising:

a semiconductor body comprising a first surface, a second surface opposite the first surface, an edge extending in a vertical direction substantially perpendicular to the first surface, an active area, a peripheral area arranged in a horizontal direction substantially parallel to the first surface between the active area and the edge, a pn-junction formed between a first semiconductor region and a second semiconductor region of the semiconductor body, the pn-junction being arranged next to the first surface and extending from the active area into the peripheral area;

a first metallization arranged on the first surface and in ohmic contact with the second semiconductor region; and

a second metallization arranged on the second surface,

wherein in the peripheral area the semiconductor device further comprises;

at least one field plate arranged on the first surface; and

a passivation structure at least partly covering the at least one field plate and comprising at a surface of the at least one field plate a varying thickness.

13. The vertical semiconductor device of claim 12, wherein the varying thickness is largest at least close to an edge of the at least one field plate.

14. The vertical semiconductor device of claim 12, wherein the varying thickness is largest where an electric field at a surface of the at least one field plate is expected to be highest when the pn-junction is reversely biased.

15. The vertical semiconductor device of claim 12, further comprising at least one of a first dielectric layer arranged between the semiconductor body and the at least one field plate, and a second dielectric layer arranged on the at least one field plate.

16. The vertical semiconductor device of claim 12, wherein a ratio between a maximum value of the varying thickness and a minimum value of the varying thickness is at least about 10.

17. A method for forming vertical semiconductor device, the method comprising:

providing a semiconductor body comprising a first surface, a second surface opposite the first surface, an active area, a peripheral area surrounding the active area, a pn-junction arranged next to the first surface and extending from the active area into the peripheral area;

forming a first dielectric layer on the first surface;

forming in the peripheral area a field plate on the first dielectric layer;

depositing a first passivation layer on the field plate; and

at least reducing a thickness of the first passivation layer at least at a portion of the field plate.

18. The method of claim 17, further comprising forming at least two field plates on the first dielectric layer, and wherein the thickness of the passivation layer is reduced such that the first passivation layer at the field plate which is closest to the edge is thinner than at another field plate.

19. The method of claim 17, further comprising at least one of:

forming an insulated gate electrode next to the pn-junction;

forming a plurality of field-effect structures in the active area next to the first surface;

forming a second passivation layer at the first passivation layer;

forming a second dielectric layer on the first passivation layer;

forming a second dielectric layer on the second passivation layer;

forming a second metallization in Ohmic contact with the field plate; and

depositing a sealing compound on the second dielectric layer.

20. The method of claim 17, wherein the first passivation layer is substantially removed from a portion of the field plate which is substantially parallel to the first surface.