CONNECTION STRUCTURE FOR VERTICAL GATE ALL AROUND (VGAA) DEVICES ON SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE

• US 20150303270A1
• Filed: 04/18/2014
• Published: 10/22/2015
• Est. Priority Date: 04/18/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIAW, JHON-JHY
• Granted Patent: US 9,653,563 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11879 Data lines (buses)
• CPC Class Codes: H01L 2027/11881 Power supply lines
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.

Claims

1. A vertical gate all around (VGAA) nanowire device circuit routing structure, the circuit routing structure comprising:

a plurality of VGAA nanowire devices including a NMOS VGAA nanowire device and a PMOS VGAA nanowire device, the VGAA nanowire devices being formed on a semiconductor-on-insulator (SOI) substrate, each of the VGAA nanowire devices comprising a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other of the bottom and top plates serves as a source node, each of the VGAA nanowire devices further comprising a gate layer, the gate layer comprising a high-K gate dielectric and a metal layer, the gate layer fully surrounding a vertical channel in the VGAA nanowire device and serving as a gate node; and

a CMOS circuit formed by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit comprising an oxide diffusion (OD) block layer that serves as a common bottom plate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device to electrically connect the drain node of the NMOS VGAA nanowire device to the drain node of the PMOS VGAA nanowire device, the CMOS circuit further comprising a first gate layer that serves as a common gate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device to electrically connect the gate node of the NMOS VGAA nanowire device to the gate node of the PMOS VGAA nanowire device, the CMOS circuit further comprising a first top plate that serves as the source node for the NMOS VGAA nanowire device and a second top plate that serves as the source node for the PMOS VGAA nanowire device, wherein the first top plate is electrically connected to a Vss conductor and the second top plate is electrically connected to a Vdd conductor.

2. The routing structure of claim 1, further comprise a silicide layer formed on the OD block layer.

3. The routing structure of claim 1, wherein each of the first top plate and the second top plate comprises a silicide layer formed on each of the first top plate and the second top plate.

4. The routing structure of claim 1, wherein the vertical channel in each of the NMOS VGAA nanowire device and the PMOS VGAA nanowire device comprises a Si-based or epi growth compound material and extends in length from the corresponding source node to the corresponding drain node.

5. The routing structure of claim 4, wherein the channel material of the PMOS VGAA nanowire device comprises a Si-based or epi growth compound material selected from a group comprising:

SiGe, SiGeC, Ge, Si, a type III-V compound, or a combination of one or more of the foregoing materials.

6. The routing structure of claim 4, wherein the channel material of the NMOS VGAA nanowire device comprises a Si-base or epi growth compound material selected from a group comprising:

SiP, SiC, SiPC, Si, Ge, a type III-V compound, or a combination of one or more of the foregoing materials.

7. The routing structure of claim 4, wherein the diameter (or width) of the nanowire vertical channel is less than 10 nm.

8. The routing structure of claim 4, wherein each of the VGAA nanowire devices comprises a plurality of vertical nano-pillar formed channel regions extending between a common drain node and a common source node and surrounded by a common gate node in the VGAA nanowire device.

15. The cell structure of claim 8, wherein the top plate comprises a silicide layer formed on the top plate layer.

16. The cell structure of claim 8, wherein each cell further comprises a first Vdd line, a first Vss line, a second Vss line, a bit-line, a bit-line bar and a word-line, the first Vdd line, wherein the bit-line and the bit-line bar are located at a first level metal layer, and wherein the first Vss line, the second Vss line and the word-line are located at second level metal layer, wherein the second level metal layer is located above the first level metal layer.

17. The cell structure of claim 8, wherein each cell further comprises a first Vdd line, a first Vss line, a second Vss line, a bit-line, a bit-line bar and a word-line, the first Vdd line, wherein the word-line is located at a first level metal layer, wherein the first Vdd line, the first Vss line, the second Vss line, the bit-line and the bit-line bar are located at a second level metal layer, and wherein the second level metal layer is located above the first level metal layer.

9. A memory cell structure, comprising:

a plurality memory cells, each memory cell comprising two cross-coupled inverters having a data storage node and a complementary data storage node, each inverter comprising a P-type VGAA nanowire pull-up (PU) device, an N-type VGAA nanowire pull-down (PD) device, and first and second pass-gate (PG) devices, each pass-gate device being an N-type VGAA nanowire device, wherein the P-type and N-type VGAA devices are formed on a semiconductor-on-insulator (SOI) substrate, each of the VGAA nanowire devices comprising a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other of the bottom and top plates serves as a source node for the VGAA nanowire device, each of the VGAA nanowire devices further comprising a gate layer, the gate layer comprising a high-K gate dielectric and a metal layer, the gate layer fully surrounding a vertical channel in the VGAA nanowire device and serving as a gate node;

each cell comprising an oxide diffusion (OD) block layer comprising two isolated OD blocks, a first OD block being a first common bottom plate of a first pull-down (PD-1) VGAA device, a first pull-up (PU-1) VGAA device and a first pass-gate (PG-1) VGAA device, a second OD block being a second common bottom plate of a second pull-down (PD-2) VGAA device, a second pull-up (PU-2) VGAA device and a second pass-gate (PG-2) VGAA device;

each cell comprising four gate layers, a first gate layer being the gate node of the first inverter, a second gate layer being the gate node of the second inverter, a third gate layer being the gate node of the first pass-gate device and a fourth gate layer being the gate node of the second pass-gate device.

10. The cell structure of claim 9, wherein each cell further comprises six silicon based top plates, a first top plate being a source node of the PD-1 VGAA device and electrically connected to a first Vss conductor, a second top plate being the source node of the PD-2 VGAA device and electrically connected to a second Vss conductor, a third top plate being the source node of the PU-1 VGAA device and electrically connected to a Vdd conductor, a fourth top plate being a source node of the PU-2 VGAA device and electrically connected to the Vdd conductor, a fifth top plate as a source node of the PG-1 VGAA device and electrically connected to a bit-line conductor, and a sixth top plate being a source node of the PG-2 VGAA device and electrically connected to the complementary bit-line conductor.

11. The cell structure of claim 10, wherein the top plates are all shared with an adjacent cell.

12. The cell structure of claim 9, further comprising a first butt connection module to electrically connect the first gate layer and the second OD block together, and a second butt connection module to electrically connect the second gate layer and the first OD block together.

13. The cell structure of claim 12, wherein the butt connection model comprises a longer contact to connect a gate to an OD block, or comprises a longer gate contact and an OD contact electrically connected together.

14. The cell structure of claim 9, further comprising a silicide layer formed on the OD block layer.

18. A vertical gate all around (VGAA) nanowire device circuit routing structure, comprising:

a plurality of VGAA nanowire devices including a NMOS VGAA nanowire device and a PMOS VGAA nanowire device, the VGAA nanowire devices having been formed on a semiconductor-on-insulator (SOI) substrate, each VGAA nanowire device comprising a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other of the bottom and top plates serves as a source node, each VGAA nanowire device further comprising a gate layer, the gate layer comprising a high-K gate dielectric and a metal layer, the gate layer fully surrounding a vertical channel in the VGAA nanowire device and serving as a gate node

a CMOS circuit formed by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit further comprising a silicon-based block as a common top plate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device to electrically connect the drain nodes of the NMOS VGAA nanowire device and the PMOS VGAA nanowire device together, the CMOS circuit comprising a gate layer that serves as a common gate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit comprising a first oxide diffusion (OD) layer that serves as the source node for the NMOS VGAA nanowire device and a second OD layer that serves as the source node for the PMOS VGAA nanowire device, wherein the first OD layer is electrically connected to a Vss conductor and the second OD layer is electrically connected to a Vdd conductor.

19. The routing structure of claim 18, wherein a silicide layer is formed on the first and second OD block layers and on the top plate layer.

20. The routing structure of claim 18, wherein the vertical channel in each VGAA nanowire device comprises a silicon-based material and extends lengthwise from a source region to a drain region in the VGAA nanowire device.