PUNCH THROUGH STOPPER IN BULK FINFET DEVICE

• US 20150303284A1
• Filed: 12/22/2014
• Published: 10/22/2015
• Est. Priority Date: 04/16/2014
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Liu, Zuoguang, Yamashita, Tenko, Yeh, Chun-Chen
• Granted Patent: US 9,559,191 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Claims

1. A method for forming a semiconductor device comprising:

forming a fin structure from a bulk semiconductor substrate;

forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed;

forming a sacrificial spacer on the upper portion of the sidewall of the fin structure;

recessing the isolation region to provide an exposed section of the lower portion of the sidewall of the fin structure;

forming a doped semiconductor material on the exposed section of the fin structure; and

diffusing dopant from the doped semiconductor material to a base portion of the fin structure.

2. The method of claim 1 further comprising forming a gate structure on a channel region portion of the fin structure after said forming the isolation region and before said forming the sacrificial spacer.

3. The method of claim 1, wherein the dopant that is diffused from the doped semiconductor material to the base portion of the fin structure has an opposite conductivity as a source region dopant and a drain region dopant.

4. The method of claim 2, wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after said diffusing the dopant from the doped semiconductor material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure.

5. The method of claim 4, wherein the forming of the replacement gate on the fin structure comprises:

depositing at least one sacrificial material layer on the fin structure; and

patterning the at least one sacrificial material layer to remove the sacrificial material from a source region portion and a drain region portion of the fin structure so that a remaining portion of the at least one sacrificial material layer is present on the channel region portion of the fin structure.

6. The method of claim 1, wherein forming the isolation region comprises:

depositing a dielectric material in contact with an entire sidewall of the fin structure; and

recessing the dielectric material to expose the upper portion of the sidewall.

7. The method of claim 1, wherein the forming of the sacrificial spacer comprises:

conformally depositing a blanket layer of a dielectric material; and

anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure.

8. The method of claim 1, wherein said forming the doped semiconductor material on the exposed section of the sidewall of the fin structure comprises epitaxial deposition of a silicon including material that is in situ doped with an n-type or p-type dopant.

9. The method of claim 1, wherein said diffusing dopant from the doped semiconductor material to a base portion of the fin structure comprises thermal annealing selected from the group consisting of rapid thermal anneal, laser annealing and combinations thereof.

10. The method of claim 1 further comprising removing the sacrificial spacer, and forming source and drain regions in contact with the upper portion of the sidewall of the fin structure.

11. A method for forming a semiconductor device comprising:

forming a fin structure from a bulk semiconductor substrate;

forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed;

forming a sacrificial spacer on the upper portion of the sidewall of the fin structure;

recessing the isolation region to provide an exposed section of the lower portion of the sidewall of the fin structure;

forming a doped semiconductor material on the exposed section of the fin structure;

diffusing dopant from the doped semiconductor material to a base portion of the fin structure;

removing the sacrificial spacer; and

forming source and drain regions in contact with the upper portion of the sidewall of the fin structure.

12. The method of claim 11 further comprising forming a gate structure on a channel region portion of the fin structure after said forming the isolation region and before said forming the sacrificial spacer.

13. The method of claim 12, wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after said diffusing the dopant from the doped semiconductor material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure.

14. The method of claim 13, wherein the forming of the sacrificial spacer comprises:

conformally depositing a blanket layer of a dielectric material; and

anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure.

15. The method of claim 13, wherein said forming the doped semiconductor material on the exposed section of the lower portion of the sidewall of the fin structure comprises epitaxial deposition of a silicon including material that is in situ doped with an n-type or p-type dopant.

16. The method of claim 11, wherein said diffusing dopant from the doped semiconductor material to a base portion of the fin structure comprises thermal annealing selected from the group consisting of rapid thermal anneal, laser annealing and combinations thereof.

17. A finFET semiconductor device comprising:

a fin structure including a channel region portion, a source region portion, a drain region portion, and a punch through stopper dopant region present at a base of the fin structure for the source region portion and the drain region portion, wherein at least one of the source region portion and the drain region portion has a stepped sidewall with a base width that is greater than a width of an upper surface of said at least one of the source region portion and the drain region portion; and

a gate structure present on the channel region portion of the fin structure.

18. The finFET semiconductor device of claim 17, wherein the fin structures are present on an etched portion of a bulk semiconductor substrate.

19. The finFET semiconductor device of claim 17, wherein the punch through stopper dopant region is doped to a conductivity type that is opposite a conductivity type of the source region portion and drain region portion of the fin structure.

20. The finFET semiconductor device of claim 17, wherein the base width ranges from 10 nm to 15 nm, and the width of the upper surface ranges from 8 nm to 10 nm.