METHOD FOR A GAN VERTICAL MICROCAVITY SURFACE EMITTING LASER (VCSEL)

• US 20150303655A1
• Filed: 04/15/2015
• Published: 10/22/2015
• Est. Priority Date: 04/16/2014
• Status: Active Grant

• Current Assignee: Yale University
• Original Assignee: Yale University
• Inventors: Han, Jung, Lin, Chia-Feng, Chen, Danti
• Granted Patent: US 11,095,096 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 33/145 with a current-blocking structure
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01S 5/04253 having specific optical properties, e.g. transparent electrodes
• CPC Class Codes: H01S 5/04257 having positive and negative electrodes on the same side of the substrate
• CPC Class Codes: H01S 5/18311 using selective oxidation
• CPC Class Codes: H01S 5/18341 Intra-cavity contacts
• CPC Class Codes: H01S 5/18347 Mesa comprising active layer
• CPC Class Codes: H01S 5/18363 comprising air layers
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

Methods and structures for forming vertical-cavity light-emitting devices are described. An n-side or bottom-side layer may be laterally etched to form a porous semiconductor region and converted to a porous oxide. The porous oxide can provide a current-blocking and guiding layer that aids in directing bias current through an active area of the light-emitting device. Distributed Bragg reflectors may be fabricated on both sides of the active region to form a vertical-cavity surface-emitting laser. The light-emitting devices may be formed from III-nitride materials.

Claims

1. A semiconductor light-emitting device comprising:

a substrate;

an active region comprising semiconductor material, wherein the active region has a first area and at least a portion of the active region is configured for carrier recombination;

a doped semiconductor region located between the active region and the substrate having a second area smaller than the first area; and

a porous oxide extending around the doped semiconductor region and located between the active region and the substrate.

2. The semiconductor light-emitting device of claim 1, wherein the active region and doped semiconductor region comprise III-nitride material.

3. The semiconductor light-emitting device of claim 2, wherein the porous oxide comprises gallium oxide, aluminum-gallium oxide, or indium-gallium oxide.

4. The semiconductor light-emitting device of claim 2, wherein the active region is configured to produce photons when electrical current flows through the active region.

5. The semiconductor light-emitting device of claim 1, wherein the porous oxide is formed in and from a same layer of material as the doped semiconductor region.

6. The semiconductor light-emitting device of claim 1, wherein the doped semiconductor region comprises n-type conductivity material.

7. The semiconductor light-emitting device of claim 1, wherein the active region comprises multiple quantum wells formed from layers of III-nitride material.

8. The semiconductor light-emitting device of claim 1, further comprising a conductive layer of semiconductor material formed between the doped semiconductor region and the substrate, wherein a doping density of the conductive layer is less than a doping density of the doped semiconductor region.

9. The semiconductor light-emitting device of claim 8, further comprising an undoped semiconductor layer between the conductive layer of semiconductor material and the substrate.

10. The semiconductor light-emitting device of claim 8, wherein a doping density of the conductive layer is between approximately 5×

10¹⁷ cm<sup>−

3</sup> and approximately 2×

10¹⁸ cm<sup>−

3</sup> and a doping density of the doped semiconductor region is between approximately 3×

10¹⁸ cm<sup>−

3</sup> and approximately 1×

10¹⁹ cm<sup>−

3</sup>.

11. The semiconductor light-emitting device of claim 1, further comprising a first distributed Bragg reflector located between the doped semiconductor region and the substrate.

12. The semiconductor light-emitting device of claim 11, wherein the first distributed Bragg reflector comprises alternating layers of air and III-nitride material.

13. The semiconductor light-emitting device of claim 11, further comprising at least one undoped semiconductor layer between the doped semiconductor region and the first distributed Bragg reflector.

14. The semiconductor light-emitting device of claim 11, further comprising:

a conductive layer having a doping density between approximately 5×

10¹⁷ cm<sup>−

3</sup> and approximately 2×

10¹⁸ cm<sup>−

3</sup> located between the doped semiconductor region and the first distributed Bragg reflector; and

an undoped semiconductor layer between the conductive layer and the first distributed Bragg reflector, wherein a doping density of the doped semiconductor region is between approximately 3×

10¹⁸ cm<sup>−

3</sup> and approximately 1×

10¹⁹ cm<sup>−

3</sup>.

15. The semiconductor light-emitting device of claim 11, further comprising a second distributed Bragg reflector located on a side of the active region away from the substrate.

16. The semiconductor light-emitting device of claim 15, wherein the second distributed Bragg reflector comprises layers of dielectric material.

17. A method for making an integrated light-emitting device, the method comprising:

forming a mesa on a substrate that comprises an active region of semiconductor material and a doped semiconductor layer located between the active region and substrate;

etching a portion of the doped semiconductor layer to form a porous semiconductor region extending around a remaining doped semiconductor region, wherein the porous semiconductor region and doped semiconductor region are located between the active region and the substrate; and

converting the porous semiconductor region to a porous oxide.

18. The method of claim 17, wherein forming the doped semiconductor layer comprises epitaxially growing an n-type conductivity layer of III-nitride material.

19. The method of claim 17, further comprising forming a conductive layer of semiconductor material adjacent the doped semiconductor layer, wherein a doping density of the conductive layer is less than a doping density of the doped semiconductor layer.

20. The method of claim 19, further comprising:

forming the doped semiconductor layer and conductive layer from III-nitride material;

doping the conductive layer with a doping density between approximately 5×

10¹⁷ cm<sup>−

3</sup> and approximately 2×

10¹⁸ cm<sup>−

3</sup>; and

doping the doped semiconductor layer with a doping density between approximately 3×

10¹⁸ cm<sup>−

3</sup> and approximately 1×

10¹⁹ cm<sup>−

3</sup>.

21. The method of claim 17, wherein the etching comprises electrochemical etching with a hydrofluoric-based etchant.

22. The method of claim 21, wherein the etching further comprises applying a bias between approximately 7 volts and approximately 20 volts between the doped semiconductor layer and an electrode in the etchant.

23. The method of claim 17, wherein converting the porous semiconductor region comprises oxidizing the porous semiconductor to form gallium oxide, aluminum-gallium oxide, or indium-gallium oxide.

24. The method of claim 17, wherein the active region is configured to produce photons when electrical current flows through the active region.

25. The method of claim 24, wherein forming the active region comprises forming multiple quantum wells from layers of III-nitride material.

26. The method of claim 17, further comprising forming a first distributed Bragg reflector located between the doped semiconductor region and the substrate.

27. The method of claim 26, wherein forming the first distributed Bragg reflector comprises:

epitaxially growing at least one layer of n-type III-nitride semiconductor material and at least one layer of undoped III-nitride semiconductor material;

etching a hole adjacent the mesa to expose sidewalls of n-type III-nitride semiconductor material; and

electrochemically etching at least a portion of the at least one layer of n-type III-nitride semiconductor material to form at least one air gap between the remaining doped semiconductor region and the substrate.

28. The method of claim 27, wherein the at least one layer of n-type III-nitride semiconductor material comprises GaN and have a doping density between approximately 8×

10¹⁸ cm<sup>−

3</sup> and approximately 5×

10¹⁹ cm<sup>−

3</sup>.

29. The method of claim 28, wherein etching a portion of the doped semiconductor layer and electrochemically etching at least a portion of the at least one layer of n-type III-nitride semiconductor material are performed in a same etching step.

30. The method of claim 26, further comprising forming at least one undoped semiconductor layer between the doped semiconductor region and the first distributed Bragg reflector.

31. The method of claim 26, further comprising forming a second distributed Bragg reflector located on a side of the active region away from the substrate.

32. The method of claim 26, wherein forming the second distributed Bragg reflector comprises depositing layers of dielectric material.