METHOD AND APPARATUS TO MITIGATE RIPPLE IN A TIME OF FLIGHT (TOF) SYSTEM

• US 20150308949A1
• Filed: 04/29/2015
• Published: 10/29/2015
• Est. Priority Date: 04/29/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sadhu, Subhash Chandra Venkata, Patil, Bharath
• Granted Patent: US 11,143,552 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 2223/506 time-of-flight
• CPC Class Codes: G01S 7/484 Transmitters
• CPC Class Codes: H05B 45/37 Converter circuits
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

The disclosure provides a circuit to mitigate ripple. The circuit includes a controller that generates a PWM (pulse width modulated) clock signal. A DC/DC converter receives the PWM clock signal, and generates an output signal. A light source is coupled to the DC/DC converter, and receives the output signal. The light source transmits light pulses during an integration time. A time integral of the output signal during the integration time is constant during a plurality of quad time periods.

Claims

1. A circuit comprising:

a controller configured to generate a PWM (pulse width modulated) clock signal;

a DC/DC converter configured to receive the PWM clock signal, and generate an output signal; and

a light source coupled to the DC/DC converter and configured to receive the output signal, the light source configured to transmit light pulses during an integration time, wherein a time integral of the output signal during the integration time is constant during a plurality of quad time periods.

2. The circuit of claim 1 further comprising a switch coupled in parallel to the light source, the switch configured to be activated by an enable signal during the integration time.

3. The circuit of claim 1, wherein each quad time period of the plurality of quad time periods includes a reset time, the integration time, a readout time and a dead time.

4. The circuit of claim 1, wherein the output signal is at least one of a voltage signal and a current signal.

5. The circuit of claim 1, wherein the time integral of the output signal during the integration time is constant during the plurality of quad time periods further comprises a time period of each quad time period of the plurality of quad time periods is a positive integer multiple of a time period of the PWM clock signal.

6. The circuit of claim 1, wherein the time integral of the output signal during the integration time is constant during the plurality of quad time periods further comprises a time difference between a positive edge of each quad time period and a positive edge of the PWM clock signal is constant.

7. The circuit of claim 1, wherein the output signal is associated with a feedback ripple having a ripple time period, and the time period of each quad time period of the plurality of quad time periods is a positive integer multiple of ripple time period.

8. The circuit of claim 1 further comprises a sensor coupled to the controller, the sensor having a plurality of pixels.

9. The circuit of claim 8, wherein each pixel of the plurality of pixels comprises:

a photodiode configured to receive reflected light pulses, and configured to generate a current signal, the light pulses are scattered by one or more objects to generate the reflected light pulses; and

a coupling capacitor coupled to the photodiode, and configured to generate a demodulated signal in response to the current signal received from the photodiode.

10. The circuit of claim 8, wherein the sensor further comprises:

a mixer coupled to the plurality of pixels, and configured to receive a synchronization signal from the controller and the demodulated signal from each pixel of the plurality of pixels, the mixer configured to generate a mixed signal;

an ADC (analog to digital converter) coupled to the mixer and configured to generate a digital signal in response to the mixed signal; and

a processor coupled to the ADC, and configured to receive the digital signal, wherein the processor is configured to generate an image of the one or more objects.

11. The circuit of claim 1, wherein during the reset time, each pixel of the plurality of pixels is reset.

12. The circuit of claim 1, wherein during the integration time, the light source transmits light pulses, and the photodiode in each pixel receives the reflected light pulses.

13. The circuit of claim 1, wherein during the readout time, the light source is disabled, and the mixer receives the demodulated signal from each pixel of the plurality of pixels.

14. The circuit of claim 1, wherein during the dead time, the light source and the ADC are disabled.

15. A method of ripple mitigation comprising:

generating a PWM clock signal;

generating an output signal in response to the PWM clock signal; and

transmitting light pulses generated by a light source during an integration time, wherein a time integral of the output signal during the integration time is constant during a plurality of quad time periods.

16. The method of claim 15, wherein a time period of each quad time period of the plurality of quad time periods is a positive integer multiple of a time period of the PWM clock signal such that the time integral of the output signal during the integration time is constant during the plurality of quad time periods.

17. The method of claim 15, wherein a time difference between a positive edge of each quad time period and a positive edge of the PWM clock signal is constant such that the time integral of the output signal during the integration time is constant during the plurality of quad time periods.

18. The method of claim 15, wherein the output signal is associated with a feedback ripple having a ripple time period, and the time period of each quad time period of the plurality of quad time periods is a positive integer multiple of ripple time period.

19. The method of claim 15 further comprising:

receiving reflected light pulses by one or more photodiodes, the light pulses are scattered by one or more objects to generate the reflected light pulses;

generating a current signal from the reflected light pulses by one or more photodiodes;

generating a demodulated signal from the current signal;

generating a mixed signal from the demodulated signal and a synchronization signal;

generating a digital signal from the mixed signal; and

processing the digital signal to generate an image of the one or more objects.

20. A TOF (time of flight) system comprising:

a controller configured to generate a PWM (pulse width modulated) clock signal;

a DC/DC converter configured to receive the PWM clock signal, and generate an output signal;

a light source coupled to the DC/DC converter, the light source configured to receive the output signal, and configured to transmit light pulses during an integration time, wherein a time integral of the output signal during the integration time is constant during a plurality of quad time periods; and

a sensor coupled to the controller, and configured to receive reflected light pulses and generate an image of one or more objects, the light pulses are scattered by the one or more objects to generate the reflected light pulses.