Memory Control System for a Non-Volatile Memory and Control Method

• US 20150309753A1
• Filed: 12/22/2014
• Published: 10/29/2015
• Est. Priority Date: 12/16/2013
• Status: Active Grant

• Current Assignee: Stichting Imec Nederland
• Original Assignee: Stichting Imec Nederland
• Inventors: Penders, Julien, Gemmeke, Tobias, Agell, Carlos
• Granted Patent: US 9,477,419 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises a memory controller that is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data. In one example, the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing. The system also includes a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation.

Claims

1. A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises:

a memory controller, which is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data, wherein the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing; and

a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation.

2. The memory control system according to claim 1, wherein the memory controller is adapted to conduct each write cycle or a set of write cycles by:

requesting to the power management unit a time period for conducting the write cycle or set of write cycles;

receiving an acknowledgement from the power management unit to conduct the write cycle or set of write cycles; and

attempting the write cycle or set of write cycles, wherein if not successful to start a new cycle or set of cycles.

3. The memory control system according to claim 1 wherein the memory controller is adapted to implement a read operation for reading at least one block of data from the memory as a sequence of memory read and validation cycles for part or all of the data, wherein the number of cycles is a function of the amount of successfully read data per cycle and is thus variable in dependence on the success of the data reading,

wherein the power management unit is adapted to authorize or prevent the memory controller from conducting the read operation at the level of the read cycles thereby to control the timing of power consumption resulting from the cycles of the read operation.

4. The memory control system according to claim 3, wherein the memory controller is adapted to conduct each read cycle or a set of read cycles by:

requesting to the power management unit a time period for conducting the read cycle or set of read cycles;

receiving an acknowledgement from the power management unit to conduct the read cycle or set of read cycles; and

attempting the read cycle or set of read cycles, wherein if not successful to start a new cycle or set of cycles.

5. A memory system, comprising:

a non-volatile memory; and

the memory control system according to claim 1 for controlling read and write access to the memory.

6. The memory system according to claim 5, wherein the non-volatile memory comprises a flash memory.

7. A device, comprising:

the memory system according to claim 5;

a main functional unit for performing a device function, wherein the power management unit is adapted to authorize or prevent in dependence on the power demand of the main functional unit.

8. The device according to claim 7, wherein the main functional unit comprises a bio-sensor and a wireless transmission module.

9. The device according to claim 8, comprising a biopotential monitoring device.

10. A method of controlling read and write operations of a non-volatile memory, comprising:

implementing a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data, wherein the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing; and

authorizing or preventing a memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation.

11. The method according to claim 10, comprising, for each write cycle or set of write cycles:

requesting to a power management unit a time period for conducting the write cycle or set of write cycles;

receiving an acknowledgement from the power management unit to conduct the write cycle or set of write cycles; and

attempting the write cycle or set of write cycles, wherein if successful reporting the success to the power management unit, and if not successful to start a new cycle or set of cycles.

12. The method according to claim 10 comprising:

implementing a read operation for reading at least one block of data from the memory as a sequence of memory read and validation cycles for part or all of the data, wherein the number of cycles is a function of the amount of successfully read data per cycle and is thus variable in dependence on the success of the data reading; and

authorizing or preventing a memory controller from conducting the read operation at the level of the read cycles thereby to control the timing of power consumption resulting from the cycles of the write operation.

13. The method according to claim 12, comprising, for each read cycle or set of read cycles:

requesting to a power management unit a time period for conducting the read cycle or set of read cycles;

receiving an acknowledgement from the power management unit to conduct the read cycle or set of read cycles;

attempting the read cycle or set of read cycles, wherein if successful, reporting the success to the power management unit, and if not successful to start a new cycle or set of cycles.

14. The method according to claim 10 for controlling read and write operations of a flash memory of a device which comprises a main functional unit for performing a device function, wherein the method comprises authorizing or preventing in dependence on the power demand of the main functional unit.

15. A biopotential monitoring method comprising writing sensed biopotential monitoring data to a memory using the method according to claim 10.