SYSTEM AND METHODS FOR DYNAMIC MANAGEMENT OF HARDWARE RESOURCES

• US 20150309802A1
• Filed: 07/06/2015
• Published: 10/29/2015
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Pattichis, Marios Stephanou, Jiang, Yuebing, Llamocca Obregon, Daniel Rolando
• Granted Patent: US 9,542,198 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: H03H 17/0241 Distributed arithmetic
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H04N 19/625 using discrete cosine transform [DCT]

Abstract

A dynamically reconfigurable framework manages processing applications in order to meet time-varying constraints to select an optimal hardware architecture. The optimal architecture satisfies time-varying constraints including for example, supplied power, required performance, accuracy levels, available bandwidth, and quality of output such as image reconstruction. The process of determining an optimal solution is defined in terms of multi-objective optimization using Pareto-optimal realizations.

Claims

1. A computer system including a processor and a memory for producing a dynamically reconfigurable framework for performing a digital video processing and/or communications task comprising the steps of:

varying by the processor one or more parameters to generate a plurality of hardware configurations and software realizations, wherein each software realization comprises software parameters including associated algorithms;

obtaining by the processor associated objective values for each hardware configuration and each software realization wherein the associated objective values are selected from;

a power measurement, a performance measurement, a video bitrate level and an accuracy measurement;

using by the processor the associated objective values to determine the hardware configurations and software realizations of the plurality that are Pareto-optimal to obtain a collection of Pareto-optimal configurations;

storing in the memory the collection of Pareto-optimal configurations and the software parameters including associated algorithms;

providing a sequence of real-time constraint optimization problems that are specified in terms of the associated objective values, wherein the real-time constraint optimization problems are selected from the group comprising;

a minimum power objective, a maximum performance objective, a maximum accuracy objective, a minimum bitrate level objective, and an objective comprising of a weighted sum of power, performance, and accuracy; and

selecting in real-time an optimal combination of the software parameters and the hardware configuration that either solves each of the real-time constraint optimization problems or minimizes violations of the real-time constraint optimization problems to obtain selected optimal combinations including selected software parameters including associated algorithms.

2. The computer system according to claim 1, wherein the hardware configuration includes one or more selected from the group consisting of:

a hardware realization in a field programmable gate array (FPGA), a graphical processing unit (GPU), a combination of multiple cores and single instruction multiple data (SIMD) extensions of a central processing unit.

3. The computer system according to claim 2, wherein the hardware configuration involving a FPGA further comprises the step of implementing in real-time each one of the selected optimal combinations by using dynamic partial reconfiguration to implement the hardware configuration in the FPGA and the selected software parameters, or by using dynamic frequency control.

4. The computer system according to claim 2, wherein the field programmable gate array is part of a pixel processor architecture.

5. The computer system according to claim 2, wherein the field programmable gate array is part of a digital filtering architecture.

6. The computer system according to claim 5, wherein the digital filtering architecture is one-dimensional.

7. The computer system according to claim 5, wherein the digital filtering architecture is two-dimensional.

8. The computer system according to claim 5, wherein the digital filtering architecture includes video compression accomplished using the Discrete Cosine Transform (DCT) hardware core that can be parameterized using a different number of bits for representing input, output, and DCT filter coefficients and a software coefficient that consists of a Quality Factor.

9. The computer system according to claim 4, wherein one or more hardware parameters of the pixel processor architecture that is used for generating the collection of Pareto-optimal hardware realizations is selected from the group comprising:

a number of cores, a number of bits of the input pixels, a number of bits of the output pixels, and a frequency of operation.

10. The computer system according to claim 5, wherein one or more hardware parameters of the digital filtering architecture are selected from the group comprising:

a number of coefficients, a number of bits representing the number of coefficients, and a number of bits for representing the output.

11. The computer system according to claim 4, wherein each pixel of the pixel processor architecture is processed independently of any other pixel.