DATA BUS DRIVING CIRCUIT, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

• US 20150309861A1
• Filed: 04/13/2015
• Published: 10/29/2015
• Est. Priority Date: 04/23/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: TAKAHASHI, Hiroyuki
• Granted Patent: US 9,740,656 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Provided is a data bus driving circuit including: a data processing unit that processes input data and outputs processed data; a first logic inversion unit that selects, based on a determination result signal, one of the processed data and inverted data obtained by logically inverting each value of a plurality of bits constituting the processed data, and outputs the selected data to a data bus; and an inversion determination unit that compares the data output from the first logic inversion unit with the input data that has not been processed by the data processing unit, and outputs the determination result signal based on a comparison result.

Claims

1. A data bus driving circuit comprising:

a data processing unit that processes input data and outputs processed data;

a first logic inversion unit that selects, based on a determination result signal, one of the processed data and inverted data obtained by logically inverting each value of a plurality of bits constituting the processed data, and outputs the selected data to a data bus; and

an inversion determination unit that compares the data output from the first logic inversion unit with the input data that has not been processed by the data processing unit, and outputs the determination result signal based on a comparison result.

2. The data bus driving circuit according to claim 1, wherein the inversion determination unit outputs the determination result signal to cause the inverted data to be output from the first logic inversion unit when the number of bits representing different logical values is greater than the number of bits representing the same logical value, as a result of comparing each value of a plurality of bits constituting the input data with each value of a plurality of bits constituting the data output from the first logic inversion unit.

3. The data bus driving circuit according to claim 2, wherein the inversion determination unit outputs the determination result signal to cause the processed data to be directly output from the first logic inversion unit when the number of bits representing different logical values is equal to or less than the number of bits representing the same logical value.

4. A semiconductor device comprising:

the data bus driving circuit according to claim 1; and

a second logic inversion unit that restores the processed data by re-inverting the inverted data based on the determination result signal, the inverted data being transmitted through the data bus.

5. The bus driving circuit according to claim 1, wherein the data processing unit serves as an ECC decoding unit that performs error correction processing on the input data based on an error correction code and outputs the corrected input data as the processed data, the input data being read out from a memory cell array.

6. A semiconductor memory device comprising:

the data bus driving circuit according to claim 5; and

the memory cell array.

7. A semiconductor device comprising:

the semiconductor memory device according to claim 6;

a logic unit; and

the data bus that connects the semiconductor memory device with the logic unit, wherein

the logic unit comprises;

a second logic inversion unit that restores the processed data by re-inverting, based on the determination result signal, the inverted data transmitted through the data bus; and

a logic circuit that receives the processed data and executes predetermined processing.

10. The data bus driving circuit according to claim 1, wherein the data processing unit is a parallel-to-serial conversion unit that converts the input data as parallel data to the processed data as serial data.

11. The data bus driving circuit according to claim 1, wherein the data processing unit is a serial-to-parallel conversion unit that converts the input data as serial data to the processed data as parallel data.

12. The data bus driving circuit according to claim 1, wherein the data processing unit serves as a storage data determination unit that outputs the input data to be written into a memory cell array as the processed data, and outputs an inversion flag signal for inverting the processed data when the number of bits representing a logical value 1 is greater than the number of bits representing a logical value 0 in a plurality of bits constituting the input data.

13. The data bus driving circuit according to claim 1, wherein the data processing unit is a noise filter.

14. The data bus driving circuit according to claim 1, wherein

the data processing unit serves as a first level shifter that converts a voltage amplitude of the input data and outputs the input data as the processed data,

the data bus driving circuit further comprises a second level shifter that restores a voltage amplitude of the data output from the first logic inversion unit to a voltage amplitude that has not been converted by the data processing unit, and

the inversion determination unit compares data output from the second level shifter with the input data that has not been processed by the data processing unit, and outputs the determination result signal based on a comparison result.

8. A semiconductor memory device comprising:

a memory cell array;

an ECC decoding unit that performs error correction processing, based on an error correction code, on data read out from the memory cell array, and outputs the corrected data;

a first logic inversion unit that selects, based on a determination result signal, one of the corrected data and inverted data obtained by logically inverting each value of a plurality of bits constituting the corrected data, and outputs the selected data to a data bus; and

an inversion determination unit that compares the data output from the first logic inversion unit with the data that has not been corrected, and outputs the determination result signal based on a comparison result.

9. A semiconductor device comprising:

the semiconductor memory device according to claim 8;

a logic unit; and

the data bus that connects the semiconductor memory device with the logic unit, wherein

the logic unit comprises;

a second logic inversion unit that restores the corrected data by re-inverting the inverted data based on the determination result signal, the inverted data being transmitted through the data bus; and

a logic circuit that receives the corrected data and executes predetermined processing.