ARITHMETIC PROCESSING APPARATUS AND METHOD FOR CONTROLLING SAME

• US 20150309934A1
• Filed: 03/30/2015
• Published: 10/29/2015
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: SUNAYAMA, Ryuichi
• Granted Patent: US 9,606,917 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0826 Limited pointers directories; State-only directories without pointers
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An arithmetic processing apparatus includes: first and second core groups each including cores, a first to an Nth (N is plural) caches that process access requests from the cores, and an intra-core-group bus through which the access requests from the cores are provided to the first to Nth caches; and a first to an Nth inter-core-group buses each provided between the first to Nth caches in the first and second core groups respectively. The first to Nth caches in the first core group individually store data from a first to an Nth memory spaces in a memory, respectively. The first to Nth caches in the second core group individually store data from an N+1th to a 2Nth memory spaces, respectively. The first to Nth caches in the first core group access the data in the N+1th to 2Nth memory spaces, respectively, via the first to Nth inter-core-group buses.

Claims

1. An arithmetic processing apparatus comprising:

a first core group and a second core group each including a plurality of arithmetic processing sections, a first to an Nth (N is a positive integer) caches that process access requests from the plurality of arithmetic processing sections, and an intra-core-group bus through which the access requests from the plurality of arithmetic processing sections are provided to the first to Nth caches; and

a first to an Nth inter-core-group buses each provided between a corresponding one of the first to Nth caches in the first core group and a corresponding one of the first to Nth caches in the second core group,

wherein the N is a plural number,

the first to Nth caches in the first core group individually store data from a first to an Nth memory spaces in a memory, respectively,

the first to Nth caches in the second core group individually store data from an N+1th to a 2Nth memory spaces in the memory, respectively,

the first to Nth caches in the first core group access the data in the N+1th to 2Nth memory spaces in the memory, respectively, via the first to Nth inter-core-group buses and store the data, and

the first to Nth caches in the second core group access the data in the first to Nth memory spaces in the memory, respectively, via the first to Nth inter-core-group buses and store the data.

2. The arithmetic processing apparatus according to claim 1, wherein, when each of the first to Nth caches in the first core group does not store latest data for the data in a corresponding one of the first to Nth memory spaces in the memory, each of the first to Nth caches in the first core group acquires the latest data from a corresponding one of the first to Nth caches in the second core group via a corresponding one of the first to Nth inter-core-group buses and stores the latest data, and

when each of the first to Nth caches in the second core group does not store latest data for the data in a corresponding one of the N+1th to 2Nth memory spaces in the memory, each of the first to Nth caches in the second core group acquires the latest data from a corresponding one of the first to Nth caches in the first core group via a corresponding one of the first to Nth inter-core-group buses and stores the latest data.

3. The arithmetic processing apparatus according to claim 1, wherein each of the first to Nth caches includes a cache tag and a cache memory,

each of the first to Nth caches in the first core group changes status information on data in the cache tag in the corresponding one of the first to Nth caches in the second core group via the corresponding one of the first to Nth inter-core-group buses, and

each of the first to Nth caches in the second core group changes status information on data in the cache tag in the corresponding one of the first to Nth caches in the first core group via the corresponding one of the first to Nth inter-core-group buses.

4. The arithmetic processing apparatus according to claim 2, wherein each of the first to Nth caches includes a cache tag and a cache memory,

each of the first to Nth caches in the first core group changes status information on data in the cache tag in the corresponding one of the first to Nth caches in the second core group via the corresponding one of the first to Nth inter-core-group buses, and

each of the first to Nth caches in the second core group changes status information on data in the cache tag in the corresponding one of the first to Nth caches in the first core group via the corresponding one of the first to Nth inter-core-group buses.

5. The arithmetic processing apparatus according to claim 1, wherein each of the first to Nth caches includes a cache tag and a cache memory,

each of the first to Nth caches in the first core group inquires about status information on data in the cache tag in the corresponding one of the first to Nth caches in the second core group via the corresponding one of the first to Nth inter-core-group buses, and acquires the status information, and

each of the first to Nth caches in the second core group inquires about status information on data in the cache tag in the corresponding one of the first to Nth caches in the first core group via the corresponding one of the first to Nth inter-core-group buses, and acquires the status information.

6. The arithmetic processing apparatus according to claim 2, wherein each of the first to Nth caches includes a cache tag and a cache memory,

each of the first to Nth caches in the first core group inquires about status information on data in the cache tag in the corresponding one of the first to Nth caches in the second core group via the corresponding one of the first to Nth inter-core-group buses, and acquires the status information, and

each of the first to Nth caches in the second core group inquires about status information on data in the cache tag in the corresponding one of the first to Nth caches in the first core group via the corresponding one of the first to Nth inter-core-group buses, and acquires the status information.

7. The arithmetic processing apparatus according to claim 4, wherein the status information includes at least a first status in which data is not stored in the cache memory, a second status in which data identical to the data in the memory is stored, and a third status in which latest data different from the data in the memory is stored.

8. The arithmetic processing apparatus according to claim 6, wherein the status information includes at least a first status in which data is not stored in the cache memory, a second status in which data identical to the data in the memory is stored, and a third status in which latest data different from the data in the memory is stored.

9. The arithmetic processing apparatus according to claim 1, wherein each of the first to Nth caches in the first core group includes a directory that holds directory information indicating whether or not the corresponding one of the first to Nth caches in the second core group stores the data from the corresponding one of the first to Nth memory spaces in the memory, and when the directory information in the directory indicates that latest data is stored, each of the first to Nth caches in the first core group acquires the latest data from the corresponding one of the first to Nth caches in the second core group via the inter-core-group bus.

10. The arithmetic processing apparatus according to claim 2, wherein each of the first to Nth caches in the first core group includes a directory that holds directory information indicating whether or not the corresponding one of the first to Nth caches in the second core group stores the data from the corresponding one of the first to Nth memory spaces in the memory, and when the directory information in the directory indicates that latest data is stored, each of the first to Nth caches in the first core group acquires the latest data from the corresponding one of the first to Nth caches in the second core group via the inter-core-group bus.

11. The arithmetic processing apparatus according to claim 9, wherein, when the directory information in the directory indicates that data identical to the data in the memory is stored, each of the first to Nth caches in the first core group acquires the data from the memory.

12. The arithmetic processing apparatus according to claim 1, wherein the first and second core groups each include a first to an Nth arithmetic processing sections,

each of the first to Nth arithmetic processing sections in the first core group registers data read from the corresponding one of the first to Nth memory spaces in the memory, in the corresponding one of the first to Nth caches in the first core group, and

each of the first to Nth arithmetic processing sections in the second core group registers data read from the corresponding one of the N+1th to 2Nth memory spaces in the memory, in the corresponding one of the first to Nth caches in the second core group.

13. A method for controlling an arithmetic processing apparatus that includes:

a first core group and a second core group each including a plurality of arithmetic processing sections, a first to an Nth (N is a positive integer) caches that process access requests from the plurality of arithmetic processing sections, and an intra-core-group bus through which the access requests from the plurality of arithmetic processing sections are provided to the first to Nth caches; and

a first to an Nth inter-core-group buses each provided between a corresponding one of the first to Nth caches in the first core group and a corresponding one of the first to Nth caches in the second core group,

the N being a plural number,

the method comprising;

individually storing, by the first to Nth caches in the first core group, data from a first to an Nth memory spaces in a memory, respectively,

individually storing, by the first to Nth caches in the second core group, data from an N+1th to a 2Nth memory spaces in the memory, respectively,

accessing and storing, by the first to Nth caches in the first core group, the data in the N+1th to 2Nth memory spaces in the memory, respectively, via the first to Nth inter-core-group buses, and

accessing and storing, by the first to Nth caches in the second core group, the data in the first to Nth memory spaces in the memory, respectively, via the first to Nth inter-core-group buses.

14. The method for controlling an arithmetic processing apparatus according to claim 13, wherein,

when each of the first to Nth caches in the first core group does not store latest data for the data in a corresponding one of the first to Nth memory spaces in the memory, each of the first to Nth caches in the first core group acquires the latest data from a corresponding one of the first to Nth caches in the second core group via a corresponding one of the first to Nth inter-core-group buses and stores the latest data, and

when each of the first to Nth caches in the second core group does not store latest data for the data in a corresponding one of the N+1th to 2Nth memory spaces in the memory, each of the first to Nth caches in the second core group acquires the latest data from a corresponding one of the first to Nth caches in the first core group via a corresponding one of the first to Nth inter-core-group buses and stores the latest data.