ARITHMETIC PROCESSING APPARATUS

• US 20150309961A1
• Filed: 03/31/2015
• Published: 10/29/2015
• Est. Priority Date: 04/28/2014
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: OZAKI, Tomoaki, MINOYA, Kenichi
• Granted Patent: US 10,083,153 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology

Abstract

An arithmetic processing apparatus performs arithmetic by a neural network in which multiple processing layers are hierarchically connected. The arithmetic processing apparatus corresponding to one of the multiple processing layers includes a convolution arithmetic portion and a pooling processing portion. The convolution arithmetic portion receives an input data from another of the plurality of processing layers, performs convolution arithmetic to the input data, and in each arithmetic cycle, outputs a part of all convolution arithmetic result data required for single pooling processing. The pooling processing portion performs the single pooling processing to the all convolution arithmetic result data before executing activation processing.

Claims

1. An arithmetic processing apparatus performing arithmetic by a neural network in which a plurality of processing layers are hierarchically connected, the arithmetic processing apparatus corresponding to one of the plurality of processing layers comprising:

a convolution arithmetic portion

receiving an input data that is input from an other of the plurality of processing layers,

performing convolution arithmetic to the input data, and,

in each arithmetic cycle, outputting a part of all convolution arithmetic result data required for single pooling processing; and

a pooling processing portion performing the single pooling processing to the all convolution arithmetic result data obtained by the convolution arithmetic portion, wherein

the pooling processing portion performs the single pooling processing before executing activation processing.

2. The arithmetic processing apparatus according to claim 1, wherein

the convolution arithmetic portion obtains a plurality of convolution arithmetic result data in a single arithmetic cycle, and

the pooling processing portion includes:

a first comparator outputting a max convolution arithmetic result data that has a largest value among the plurality of convolution arithmetic result data; and

a second comparator outputting a pooling arithmetic result data that has a largest value among a plurality of max convolution arithmetic result data, which are obtained by the first comparator in a plurality of arithmetic cycles.

3. The arithmetic processing apparatus according to claim 1, wherein

the pooling processing portion includes:

a first adder outputting a first addition data obtained by adding a plurality of convolution arithmetic result data, which are obtained by the convolution arithmetic portion in a single arithmetic cycle;

a second adder outputting a cumulative addition data obtained by cumulatively adding a plurality of the first addition data, which are obtained by the first adder in a plurality of arithmetic cycles; and

a divider outputting a pooling arithmetic result data obtained by dividing the cumulative addition data output from the second adder by a predetermined value.

4. The arithmetic processing apparatus according to claim 1, wherein

the convolution arithmetic portion includes a plurality of convolution arithmetic blocks,

the plurality of convolution arithmetic blocks include different kinds of the plurality of convolution arithmetic blocks,

the different kinds of the plurality of convolution arithmetic blocks are arranged alternately, and

the plurality of convolution arithmetic blocks shares the input data that is input from the other of the plurality of processing layers and shares a weight coefficient used in the convolution arithmetic.

5. The arithmetic processing apparatus according to claim 4, wherein

the convolution arithmetic portion includes:

an input path receiving a data that is output from a convolution arithmetic block in an other arithmetic processing apparatus;

an adder adding a data that is output from one of the plurality of convolution arithmetic blocks in the arithmetic processing apparatus and the data received through the input path and generating a convolution arithmetic result data; and

an output path outputting the convolution arithmetic result data added by the adder to an other arithmetic processing apparatus.

6. The arithmetic processing apparatus according to claim 4, wherein

the convolution arithmetic portion includes a plurality of weight coefficient memories storing a plurality of weight coefficients used in convolution arithmetic,

the plurality of weight coefficient memories are arranged from an input side that receives the input data from the other of the plurality of processing layers to an output side that outputs a convolution arithmetic result data, and

the arithmetic processing apparatus further comprises:

a read path receiving a data from an portion outside the arithmetic processing apparatus and providing the data to one of the plurality of weight coefficient memories, which is positioned closest to the input side among the plurality of weight coefficient memories; and

a transfer path transmitting the data that has input to the one of the plurality of weight coefficient memories to an other of the plurality of weight coefficient memories positioned to the output side from the one of the plurality of weight coefficient memories.