DEVICE FOR THE HARDWARE DETECTION OF LOCAL EXTREMES IN AN IMAGE

• US 20150310298A1
• Filed: 10/08/2013
• Published: 10/29/2015
• Est. Priority Date: 10/08/2012
• Status: Active Grant

• Current Assignee: Consejo Superior de Investigaciones Científicas,, Universidad de Sevilla
• Original Assignee: Conesjo Superior De Investigaciones Cientificas , Universidad de Sevilla
• Inventors: FERNNDEZ BERNI, Jorge, RODRGUEZ VZQUEZ, ngel, CARMONA GALN, Ricardo
• Granted Patent: US 9,311,559 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06V 10/36 Applying a local operator, i.e. means to operate on image points situated in the vicinity of a given point; Non-linear local filtering operations, e.g. median filtering
• CPC Class Codes: G06V 10/955 using specific electronic processors

Abstract

A device and method for the hardware detection of local edges in an image, comprised of a plurality of elemental cells for mixed signal processing, locally interconnected with each other, comprising in each cell a first switch configured to enable the pre-charging of a condenser at the supply voltage; and where once said condenser is pre-charged, it discharges via a second switch connected to a power source which varies in a monotonically increasing manner with the analogue voltage representing the value of the pixel concerned; and where the value of the pixel is compared asynchronously with the neighbouring pixels of the neighbouring cells via two inverters, a digital NOR gate, a digital NAND gate, a third and fourth switch and a memory feature to store the result.

Claims

1. A device for the hardware detection of local edges in an image with at least a pixel, comprising a plurality of elemental cells for mixed signal processing, locally interconnected in such a way that each cell is only interconnected with its eight neighbouring cells, there being no direct interaction beyond this periphery, and each cell further comprising at least one first switch configured to enable the pre-charging of a condenser at the supply voltage;

where once said condenser is pre-charged, it discharges via a second switch connected to a current source which varies in a monotonically increasing manner with the analogue voltage representing the value of the pixel concerned;

where the value of the pixel is compared asynchronously with the neighbouring pixels of the neighbouring cells via;

a first inverter fitted with at least an input, an output and an input threshold voltage,

a second inverter fitted with at least an input and an output,

a digital NOR gate fitted with at least an input and an output,

a digital NAND gate fitted with at least an input and an output,

a third and fourth switch, and

a memory feature fitted with at least two inputs and two outputs, wherein one of the inputs is an input of a clock, to store the result.

2. The device of claim 1, wherein the first and second inverters bring about a change in the output of the second inverter exactly at the instant in time when the discharge of the condenser causes its voltage to cross an input threshold voltage of the first inverter.

3. The device of claim 1, wherein the output of the second inverter is connected to the input of the corresponding digital NOR and NAND gates of its neighbouring cells.

4. The device of claim 1, wherein the output of the second inverter is connected to the input of a memory feature.

5. The device of claim 1, wherein the digital NOR gate enables by means of the activation of the third switch the determination of whether its associated pixel value constitutes a local minimum.

6. The device of claim 1, wherein the output of the NOR gate is connected to the input of the clock of the memory feature by means of the activation of the third switch to carry out the determination of whether its associated pixel value constitutes a local minimum.

7. The device of claim 1, wherein the digital NAND gate enables by means of the activation of the fourth switch the determination of whether its associated pixel value constitutes a local maximum.

8. The device of claim 1, wherein the output of the NAND gate is connected to the input of the clock of the memory feature by means of the activation of the fourth switch to carry out the determination of whether its associated pixel value constitutes a local maximum.

9. A method for the hardware detection of local edges in an image with at least a pixel, comprising a plurality of elemental cells for mixed signal processing, locally interconnected with each other in such a way that each cell is only interconnected with its eight neighbouring cells, there being no direct interaction beyond this periphery, which further comprising:

a first stage of pre-charging a condenser and its subsequent discharge via a

current source dependent on the voltage representing the pixel concerned;

a second stage where said discharge is compared constantly with that produced in the neighbouring pixels via digital logical gates, a NOR gate for calculation of the minima and a NAND gate for calculation of the maxima; and

where the result of said comparison is stored in a memory feature whose digital output will be read appropriately in accordance with the type of edge to be detected.