EQUIVALENT FUSE CIRCUIT FOR A ONE-TIME PROGRAMMABLE READ-ONLY MEMORY ARRAY

• US 20150310930A1
• Filed: 04/23/2014
• Published: 10/29/2015
• Est. Priority Date: 04/23/2014
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: BOLDT, JUERGEN, HAY, STEPHAN
• Granted Patent: US 9,564,243 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/006 on road vehicles, e.g. automobiles or trucks testing of ignition installations peculiar to internal combustion engines F02P17/00
• CPC Class Codes: G01R 31/327 Testing of circuit interrupters, switches or circuit-breakers
• CPC Class Codes: G01R 31/74 Testing of fuses
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

Technologies are provided for measuring a programming current (PC) for a memory cell (MC) of a one-time programmable read-only memory array. The MC includes a fuse equivalent circuit (FEC) that includes a first current path (CP) having a first node, a second CP having a fuse of the memory cell and a second node, and a third CP. The PC is split into a first current, a second current and a third current that flow over the first CP, the second CP, and the third CP, respectively. A first voltage applied along the first path is divided to generate a second voltage at the first node, and an output voltage generated by an operational amplifier controls the second current to maintain a third voltage at the second node at substantially the same value as the second voltage so that the second current has a sufficiently low value and does not burn the fuse.

Claims

1. A one-time programmable read-only memory array, comprising:

a memory cell, comprising;

a first transistor; and

a fuse equivalent circuit configured to receive a programming current and configured to output the programming current to the first transistor, the fuse equivalent circuit comprising;

a voltage divider configured to divide a first voltage to generate a second voltage;

an operational amplifier comprising;

a first input configured to receive a third voltage, and an output that is configured to generate an output voltage;

a current mirror configured to receive the output voltage and configured to generate a first current; and

a fuse, coupled to the first transistor and the voltage divider, the fuse being configured to receive the first current, wherein the output voltage generated by the operational amplifier controls the first current to maintain the third voltage at substantially the same value as the second voltage.

2. A one-time programmable read-only memory array according to claim 1, wherein the first current generated by the current mirror has a sufficiently low value such that the fuse does not burn when the first current flows through the fuse.

3. A one-time programmable read-only memory array according to claim 1, wherein the operational amplifier further comprises:

a second input coupled to the voltage divider, and wherein the voltage divider is coupled to the current mirror.

4. A one-time programmable read-only memory array according to claim 3, wherein the voltage divider comprises:

a first resistor coupled to a second resistor, wherein the voltage divider divides the first voltage to generate the second voltage that is less than the first voltage, wherein a first resistance value of the first resistor is greater than a second resistance value of the second resistor.

5. A one-time programmable read-only memory array according to claim 1, wherein the current mirror receives the output voltage generated by the output of the operational amplifier and generates the first current, and wherein the current mirror comprises:

a first P-channel MOSFET comprising a first gate having a first width-to-length value, and being configured to generate the first current; and

a second P-channel MOSFET comprising a second gate having a second width-to-length value, and being configured to generate a second current,

wherein the output voltage generated by the operational amplifier is applied to the first and second gates of the first P-channel MOSFET and the second P-channel MOSFET to control the first current generated by the first P-channel MOSFET to maintain the third voltage at substantially the same value as the second voltage.

6. A one-time programmable read-only memory array according to claim 5, wherein a ratio of the first current to the second current is determined based on a ratio of the first gate width-to-length value of the first P-channel MOSFET to the second gate width-to-length value of the second P-channel MOSFET.

7. A one-time programmable read-only memory array according to claim 6, wherein the first current generated by the first P-channel MOSFET is substantially less than the second current generated by the second P-channel MOSFET such that the first current that flows through the fuse is sufficiently small enough to prevent the fuse from burning.

8. A one-time programmable read-only memory array according to claim 6, wherein the second gate width-to-length value of the second P-channel MOSFET is greater than the first gate width-to-length value of the first P-channel MOSFET.

9. A one-time programmable read-only memory array according to claim 1, further comprising:

a second memory cell comprising an unburned fuse having an impedance, wherein an impedance of the fuse equivalent circuit is the substantially same as the impedance of the unburned fuse.

10. A system for testing a one-time programmable read-only memory array, the system comprising:

a programming voltage source that is configured to generate a programming current; and

a current meter configured to measure the programming current;

a bit line driver,

wherein the one-time programmable read only memory array, comprising;

a bit line coupled to the bit line driver;

a word line;

a memory cell coupled to the bit line driver, the memory cell comprising;

a first transistor coupled to the word line; and

a fuse equivalent circuit configured to receive the programming current and to output the programming current to the first transistor, the fuse equivalent circuit comprising;

a voltage divider configured to divide a first voltage to generate a second voltage, wherein a first current flows through the voltage divider;

an operational amplifier comprising;

a first input configured to receive a third voltage;

a second input coupled to the voltage divider; and

an output configured to generate an output voltage;

a current mirror coupled to;

the bit line driver, the voltage divider and the output of the operational amplifier, wherein the current mirror is configured to receive the output voltage and configured to generate a second current; and

a fuse coupled to the first transistor and to the voltage divider, wherein the fuse is configured to receive the second current, wherein the output voltage controls the second current to maintain the third voltage at substantially the same value as the second voltage.

11. A system for testing a one-time programmable read-only memory array according to claim 10, wherein the second current has a sufficiently low value such that the fuse does not burn when the second current flows through the fuse.

12. A system for testing a one-time programmable read-only memory array according to claim 10, wherein the voltage divider comprises:

a first resistor coupled to a second resistor, wherein the voltage divider is configured to divide the first voltage to generate the second voltage that is less than the first voltage.

13. A system for testing a one-time programmable read-only memory array according to claim 12, wherein a first resistance value of the first resistor is greater than a second resistance value of the second resistor.

14. A system for testing a one-time programmable read-only memory array according to claim 10, wherein the current mirror comprises:

a first P-channel MOSFET comprising a first gate having a first gate width-to-length value, and being configured to generate the second current; and

a second P-channel MOSFET comprising a second gate having a second gate width-to-length value, and being configured to generate the third current,

wherein the output voltage is applied to the first and second gates of the first P-channel MOSFET and the second P-channel MOSFET to control the second current generated by the first P-channel MOSFET to maintain the third voltage at substantially the same value as the second voltage.

15. A system for testing a one-time programmable read-only memory array according to claim 14, wherein a ratio of the second current to the third current is determined based on a ratio of the first gate width-to-length value of the first P-channel MOSFET to the second gate width-to-length value of the second P-channel MOSFET.

16. A system for testing a one-time programmable read-only memory array according to claim 15, wherein the second current generated by the first P-channel MOSFET is substantially less than the third current generated by the second P-channel MOSFET such that the second current that flows through the fuse is sufficiently small to prevent the fuse from burning.

17. A system for testing a one-time programmable read-only memory array according to claim 15, wherein the second gate width-to-length value of the second P-channel MOSFET is greater than the first gate width-to-length value of the first P-channel MOSFET.

18. A system for testing a one-time programmable read-only memory array according to claim 10, wherein the one-time programmable read-only memory array further comprises:

a second memory cell comprising an unburned fuse having an impedance, wherein an impedance of the fuse equivalent circuit is the substantially same as the impedance of the unburned fuse.

19. A method for measuring a programming current of a one-time programmable read-only memory array, the method comprising:

splitting the programming current into a first current that flows over a first current path of a fuse equivalent circuit, a second current that flows over a second current path of the fuse equivalent circuit that includes a fuse of the memory cell, and a third current that flows over a third current path of the fuse equivalent circuit;

dividing a first voltage applied along the first path to generate a second voltage at a first node located along the first path; and

generating an output voltage that controls the second current to maintain a third voltage at a second node along the second path at substantially the same value as the second voltage so that the second current has a sufficiently low value and the fuse does not burn when the second current flows through the fuse.

20. A method according to claim 19, wherein the one-time programmable read-only memory array further comprises:

a second memory cell comprising an unburned fuse having an impedance, wherein an impedance of the fuse equivalent circuit is the substantially same as the impedance of the unburned fuse.