MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE

• US 20150311199A1
• Filed: 04/29/2014
• Published: 10/29/2015
• Est. Priority Date: 04/29/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Bouche, Guillaume, Wei, Andy Chih-Hung
• Granted Patent: US 10,700,170 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate;

a plurality of fins formed in the semiconductor substrate;

a gate disposed over the plurality of fins;

a plurality of contacts in direct physical contact with the gate and directly over the plurality of fins; and

a metallization line disposed over the plurality of contacts, wherein the metallization line is in electrical contact with the plurality of contacts.

2. The semiconductor structure of claim 1, wherein the plurality of fins ranges from 20 fins to 30 fins.

3. The semiconductor structure of claim 1, wherein the plurality of fins ranges from 31 fins to 60 fins.

4. The semiconductor structure of claim 1, wherein the plurality of fins ranges from 61 fins to 200 fins.

5. The semiconductor structure of claim 1, wherein the plurality of fins are comprised of silicon.

6. The semiconductor structure of claim 1, wherein the plurality of fins are comprised of silicon germanium.

7. The semiconductor structure of claim 1, further comprising a dielectric layer disposed between the metallization line and the gate.

8. The semiconductor structure of claim 7, wherein the dielectric layer is comprised of silicon oxide.

9. The semiconductor structure of claim 1, wherein the metallization line is comprised of copper.

10. The semiconductor structure of claim 1, wherein the plurality of contacts are comprised of tungsten.

11. The semiconductor structure of claim 1, further comprising a fin merge semiconductor region.

12. The semiconductor structure of claim 11, wherein the fin merge semiconductor region comprises silicon.

13. The semiconductor structure of claim 11, wherein the fin merge semiconductor region comprises silicon germanium.

14. A semiconductor integrated circuit comprising:

a plurality of In-Out (IO) circuits, wherein each 10 circuit comprises at least one finFET device, wherein the at least one finFET device comprises a gate having a length/width aspect ratio ranging from 16 to 60.

15. The semiconductor integrated circuit of claim 14, wherein the semiconductor integrated circuit further comprises a metallization line disposed above, and in line with, the gate, wherein the metallization line has a resistance value less than a resistance value of the gate.

16. The semiconductor integrated circuit of claim 15, wherein a plurality of contacts spaced at regular intervals connect the gate to the metallization line.

17. A semiconductor structure, comprising:

a semiconductor substrate;

a plurality of fins formed in the semiconductor substrate;

a gate disposed over the plurality of fins, wherein the plurality of fins comprises between 40 fins and 100 fins;

a plurality of contacts in direct physical contact with the gate and directly over the plurality of fins, wherein a fins per contact parameter ranges from 5 fins to 20 fins; and

a metallization line disposed over the plurality of contacts, wherein the metallization line is in electrical contact with the plurality of contacts.

18. The semiconductor structure of claim 17, wherein the metallization line is comprised of copper.

19. The semiconductor structure of claim 18, wherein the plurality of contacts are comprised of tungsten.

20. The semiconductor structure of claim 19, further comprising a dielectric layer disposed between the metallization line and the gate.