ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

• US 20150311232A1
• Filed: 11/28/2013
• Published: 10/29/2015
• Est. Priority Date: 08/30/2013
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.), Ordos Equipment Manufacturing Base
• Original Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: SUN, Jian, LI, Cheng, RYU, Bongyeol, AN, Seongjun
• Application Number:
  US14/369,320
• Publication Number:
  US 20150311232A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

The invention discloses an array substrate and a manufacturing method thereof and a display device, which can solve the problems such as complicated, high cost, time-consuming process in the prior art, and increase the storage capacitance. In the array substrate, data lines and a common electrode line are provided in the same layer on the base substrate and below an active layer, the data lines and the common electrode line are provided separately, the common electrode is provided with a connection part which partly overlaps with the common electrode line in an orthographic projection direction, and the common electrode is electrically connected to the common electrode line through a first via between the connection part and the common electrode line.

Claims

1-19. -19. (canceled)

20. An array substrate comprising a base substrate and data lines and scan lines provided on the base substrate, the data lines and the scan lines define pixel regions, each of the pixel regions is provided with a thin film transistor, a common electrode and a common electrode line thereinside, the thin film transistor comprises a gate electrode, a source electrode, a drain electrode and an active layer, the gate electrode is provided above the active layer, and the source electrode and the drain electrode are provided on opposite sides of the active layer respectively, wherein

the data line and the common electrode line are provided in the same layer on the base substrate and below the active layer, the data line and the common electrode line are provided separately, the common electrode is provided with a connection part which at least partly overlaps with the common electrode line in an orthographic projection direction, and the common electrode is electrically connected to the common electrode line through a first via between the connection part and the common electrode line.

21. The array substrate according to claim 20, wherein the data line is made of the same conductive material as the common electrode line.

22. The array substrate according to claim 20, wherein the active layer is made of a low temperature poly-silicon material, the source electrode and the drain electrode are formed on the opposite sides of the active layer by ion implantation, and the common electrode line is formed below the drain electrode.

23. The array substrate according to claim 22, further comprising a buffer layer which is provided below the active layer and above the base substrate, and covers the data line and the common electrode line.

24. The array substrate according to claim 23, further comprising a gate insulating layer provided above the active layer and below the gate electrode.

25. The array substrate according to claim 24, further comprising an intermediate dielectric layer provided above the gate electrode.

26. The array substrate according to claim 25, wherein a second via is provided in positions of the buffer layer, the gate insulating layer and the intermediate dielectric layer corresponding to the data line, a third via is provided in positions of the gate insulating layer and the intermediate dielectric layer corresponding to the source electrode, and the data line is electrically connected to the source electrode through the second via and the third via.

27. The array substrate according to claim 26, further comprising a pixel electrode provided on the intermediate dielectric layer and a passivation layer provided between the pixel electrode and the common electrode, the pixel electrode partly overlaps with the common electrode in the orthographic projection direction;

and

the common electrode is provided above the passivation layer, the pixel electrode is provided below the passivation layer, a forth via is provided in positions of the gate insulating layer and the intermediate dielectric layer corresponding to the drain electrode, the pixel electrode is electrically connected to the drain electrode through the forth via, the common electrode is slit-shaped, the pixel electrode is plate-shaped or slit-shaped, and the first via between the connection part and the common electrode line penetrates through the buffer layer, the gate insulating layer, the intermediate dielectric layer and the passivation layer;

or the common electrode is provided below the passivation layer, the pixel electrode is provided above the passivation layer, a forth via is provided in positions of the gate insulating layer and the intermediate dielectric layer corresponding to the drain electrode, a fifth via is provided in a position of the passivation layer corresponding to the drain electrode, the pixel electrode is electrically connected to the drain electrode through the forth via and the fifth via, the common electrode is plate-shaped or slit-shaped, the pixel electrode is slit-shaped, and the first via between the connection part and the common electrode line penetrates through the buffer layer, the gate insulating layer, the intermediate dielectric layer.

28. The array substrate according to claim 25, further comprising a light blocking metal layer which is provided in the same layer as the data line and the common electrode line on the base substrate, and is provided below the active layer and at least partly overlaps with the active layer in the orthographic projection direction.

29. The array substrate according to claim 28, wherein the light blocking metal layer is provided between regions corresponding to the source electrode and the drain electrode, and at least partly overlaps with the gate electrode in the orthographic projection direction.

30. The array substrate according to claim 20, wherein the active layer is provided with lightly doped drain electrodes, which are provided between the source electrode and the drain electrode and at opposite sides of a region corresponding to the gate electrode.

31. A display device comprising the array substrate according to claim 20.

32. A manufacturing method of an array substrate, comprising a step of forming data lines, scan lines, common electrodes and common electrode lines and a step of forming thin film transistors, the step of forming a thin film transistor comprises a step of forming a gate electrode, a source electrode, a drain electrode and an active layer, and each of pixel regions defined by the scan lines and the data lines has a common electrode, a common electrode line and a thin film transistor, wherein

the data line and the common electrode line are provided in the same layer on the base substrate and below the active layer, the common electrode is provided with a connection part which at least partly overlaps with the common electrode line in an orthographic projection direction, the common electrode is electrically connected to the common electrode line through a first via between the connection part and the common electrode line.

33. The manufacturing method of an array substrate according to claim 32, specifically comprising:

forming a pattern containing the data line and the common electrode line, which are provided separately, on the base substrate by using a patterning process;

forming a buffer layer and a pattern containing the active layer, wherein the buffer layer covers the data line and the common electrode line, and the pattern containing the active layer is formed on the buffer layer;

forming a gate insulating layer and a pattern containing the gate electrode; and

forming a pattern containing the source electrode and the drain electrode, wherein the source electrode and the drain electrode are formed on opposite sides of the active layer by ion implantation.

34. The manufacturing method of an array substrate according to claim 33, further comprising following steps of forming the common electrode, the connection part and a pixel electrode:

forming an intermediate dielectric layer and a pattern containing the first via, a second via, a third via and a forth via, wherein the first via is formed between the connection part and the common electrode line and penetrates through the buffer layer, the gate insulating layer and the intermediate dielectric layer, the second via is formed in a position corresponding to the data line and penetrates through the buffer layer, the gate insulating layer and the intermediate dielectric layer, the third via is formed in a position corresponding to the source electrode and penetrates through the gate insulating layer and the intermediate dielectric layer, and the forth via is formed in a position corresponding to the drain electrode and penetrates through the gate insulating and the intermediate dielectric layer;

forming a pattern containing the common electrode and the connection part, wherein the first via, the second via, the third via and the forth via are filled with a conductive material used for forming the common electrode, the connection part is electrically connected to the common electrode line through the first via, and the data line is electrically connected to the source electrode through the second via and the third via;

forming a passivation layer and forming a pattern containing a fifth via in the passivation layer, wherein the fifth via is formed in a position corresponding to the drain electrode, and the position of the fifth via corresponds to that of the forth via; and

forming a pattern containing the pixel electrode, wherein the fifth via is filled with a conductive material used for forming the pixel electrode, and the pixel electrode is electrically connected to the drain electrode through the forth via and the fifth via.

35. The manufacturing method of an array substrate according to claim 33, further comprising following steps of forming the common electrode, the connection part and a pixel electrode:

forming an intermediate dielectric layer and a pattern containing a second via, a third via and a forth via, wherein the second via is formed in a position corresponding to the data line and penetrates through the buffer layer, the gate insulating layer and the intermediate dielectric layer, the third via is formed in a position corresponding to the source electrode and penetrates through the gate insulating layer and the intermediate dielectric layer, and the forth via is formed in a position corresponding to the drain electrode and penetrates through the gate insulating layer and the intermediate dielectric layer;

forming a pattern containing the pixel electrode, wherein the second via, the third via and the forth via are filled with a conductive material used for forming the common electrode, the data line is electrically connected to the source electrode through the second via and the third via, and the pixel electrode is electrically connected to the drain electrode through the forth via;

forming a passivation layer and a pattern containing the common electrode and the connection part, wherein the passivation layer covers the pixel electrode, the pattern containing the common electrode and the connection part is formed above the passivation layer; and

forming the first via between the connection part and the common electrode line, wherein the first via penetrates through the buffer layer, the gate insulating layer, the intermediate dielectric layer and the passivation layer.

36. The manufacturing method of an array substrate according to claim 33, the step of forming the source electrode and the drain electrode comprises forming lightly doped drain electrodes in the active layer by ion implantation, wherein the lightly doped drain electrodes are formed between the source electrode and the drain electrode and on opposite sides of a region corresponding to the gate electrode.

37. The manufacturing method of an array substrate according to claim 33, wherein the step of forming a pattern containing the data line and the common electrode line comprises:

forming a light blocking metal layer on the base substrate so that the light blocking metal layer is provided in the same layer as the data line and the common electrode line, is provided below the active layer and at least partly overlaps with the active layer in the orthographic projection direction.

38. The manufacturing method of an array substrate according to claim 34, wherein the step of forming a pattern containing the data line and the common electrode line comprises:

forming a light blocking metal layer on the base substrate so that the light blocking metal layer is provided in the same layer as the data line and the common electrode line, is provided below the active layer and at least partly overlaps with the active layer in the orthographic projection direction.

39. The manufacturing method of an array substrate according to claim 37, wherein at least one light blocking metal layer is formed in the step of forming a pattern containing the data line and the common electrode line, at least one gate electrode is formed in the step of forming the gate insulating layer and a pattern containing the gate electrode, and the light blocking metal layer is formed in a position corresponding to that of the gate electrode.