ITC-IGBT AND MANUFACTURING METHOD THEREFOR

• US 20150311327A1
• Filed: 12/06/2012
• Published: 10/29/2015
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences, Jiangsu Cas-Igbt Technology Co., Ltd., Shanghai Lianxing Electronics Co., Ltd.
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences, Jiangsu Cas-Igbt Technology Co., Ltd., Shanghai Lianxing Electronics Co., Ltd.
• Inventors: WU, Zhenxing, ZHU, Yangjun, TIAN, Xiaoli, LU, Shuojin
• Granted Patent: US 9,590,083 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0817 of heterojunction bipolar transistors H01L29/7375 takes precedence
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

An ITC-IGBT and a manufacturing method therefor. The method comprises: providing a heavily doped substrate, forming a Ge_xSi_1-x/Si multi-quantum well strained super lattice layer on the surface of the heavily doped substrate, and forming a lightly doped layer on the surface of the Ge_xSi_1-x/Si multi-quantum well strained super lattice layer. The Ge_xSi_1-x/Si multi-quantum well strained super lattice layer is formed on the surface of the heavily doped substrate through one step, simplifying the production process of the ITC-IGBT.

Claims

1. A method for fabricating an ITC-IGBT, comprising:

preparing a heavily doped substrate;

forming a Ge_xSi_1-x/Si multiple quantum well strained superlattice layer on a surface of the heavily doped substrate by means of the molecular beam epitaxy process; and

forming a lightly doped layer on a surface of the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer.

2. The method according to claim 1, wherein after the process of forming a Ge_xSi_1-x/Si multiple quantum well strained superlattice layer, the method further comprises:

annealing the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer by means of the high temperature annealing process.

3. The method according to claim 2, wherein the annealing temperature for the high temperature annealing process ranges from 700 Celsius degrees to 800 Celsius degrees.

4. The method according to claim 1, wherein the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer has a thickness of 5 μ

m to 10 μ

m.

5. The method according to claim 1, wherein the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer comprises 50 cycles to 100 cycles of Ge_xSi_1-x/Si strained superlattice layers.

6. The method according to claim 1, wherein the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer is N-type doped, with a doping concentration ranging from 1e¹³ cm⁻

3 to 5e¹³ cm<sup>−

3</sup>.

7. The method according to claim 1, wherein after the process of forming a lightly doped layer, the method further comprises:

forming a front structure of the ITC-IGBT on the lightly doped layer; and

forming a rear structure of the ITC-IGBT on a rear surface of the highly doped substrate.

8. The method according to claim 7, wherein the process of forming a front structure of the ITC-IGBT on the lightly doped layer comprises:

forming a trench in a surface of the lightly doped layer by means of the laser etching process;

forming a first gate dielectric layer on a bottom and sidewalls of the trench;

forming a trench gate in the trench, wherein the trench gate fills up the trench;

forming a second gate dielectric layer on a surface of the trench gate;

forming a well region in the surface of the lightly doped layer by means of the ion implantation process and the high temperature annealing process, wherein a surface of the well region is flush with the surface of the lightly doped layer;

forming an emitter region in the well region by means of the ion implantation process and the high temperature annealing process, wherein a surface of the emitter region is flush with the surface of the lightly doped layer; and

forming an emitter on the surface of the well region and the surface of the emitter region and forming a gate on the surface of the trench gate by etching the second gate dielectric layer.

9. The method according to claim 7, wherein the process of forming a rear structure of the ITC-IGBT on a rear surface of the highly doped substrate comprises:

thinning the highly doped substrate by means of the chemical-mechanical polish process to form a collector region;

forming a collector on a rear surface of the collector region.

10. The method according to claim 8, wherein the highly doped substrate is highly P-type doped, the lightly doped layer is lightly N-type doped, the well region is P-type doped and the emitter region is highly N-type doped.

11. An ITC-IGBT, comprising:

a collector region;

a Ge_xSi_1-x/Si multiple quantum well strained superlattice layer located on a surface of the collector region; and

a lightly doped layer located on a surface of the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer.

12. The ITC-IGBT according to claim 11, wherein the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer has a thickness of 5 μ

m to 10 μ

m.

13. The ITC-IGBT according to claim 11, wherein the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer comprises 50 cycles to 100 cycles of Ge_xSi_1-x/Si strained superlattice layers.

14. The ITC-IGBT according to claim 11, wherein the Ge_xSi_1-x/Si multiple quantum well strained superlattice layer is N-type doped, with a doping concentration ranging from 1e¹³ cm⁻

3 to 5e¹³ cm<sup>−

3</sup>.

15. The ITC-IGBT according to claim 11, further comprising:

a front structure of the ITC-IGBT located on the lightly doped layer; and

a collector located on a rear surface of the collector region.

16. The ITC-IGBT according to claim 15, wherein the front structure of the ITC-IGBT comprises:

a trench located in a surface of the lightly doped layer;

a first gate dielectric layer located on a bottom and sidewalls of the trench;

a trench gate located in the trench, wherein the trench gate fills up the trench;

a second gate dielectric layer wrapping a surface of the trench gate;

a well region located in the surface of the lightly doped layer, wherein a surface of the well region is flush with the surface of the lightly doped layer;

an emitter region located in the well region, wherein a surface of the emitter region is flush with the surface of the lightly doped layer; and

an emitter located on the surface of the well region and the surface of the emitter region and a gate located on the surface of the trench gate.

17. The ITC-IGBT according to claim 16, wherein the collector region is highly P-type doped, the lightly doped layer is lightly N-type doped, the well region is P-type doped and the emitter region is highly N-type doped.