Cascaded multi-level Power converter

• US 20150311776A1
• Filed: 01/16/2014
• Published: 10/29/2015
• Est. Priority Date: 01/29/2013
• Status: Active Grant

• Current Assignee: Schneider Toshiba Inverter Europe SAS (Toshiba Corporation)
• Original Assignee: Schneider Toshiba Inverter Europe SAS (Toshiba Corporation)
• Inventors: LAVIEVILLE, Jean-Paul
• Granted Patent: US 9,735,664 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 1/0095 Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4833 Capacitor voltage balancing
• CPC Class Codes: H02M 7/4837 Flying capacitor converters
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters

Abstract

The invention relates to a multi-level power converter comprising:—n input stages (Ein_n), n being at least equal to 1, each input stage comprising n+1 identical input converters (CONVx_En) connected together, the input converters (CONVx_En) exhibiting an identical topology, chosen from among the architectures of the NPC (Neutral point Clamped), ANPC (Active Neutral Point Clamped), NPP (Neutral Point Piloted) and SMC (Stacked Multicell Converter),—an output stage (Eout) connected to the input stage of rank 1 and comprising an output converter (CONVs) supplied with a differential voltage (Vfloat) resulting from a first electrical potential applied to the output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to the output of a second input converter of the input stage of rank 1, the output converter (CONVs) exhibiting a topology chosen from among an architecture with floating capacitor (FC), SMC (Stacked Multicell Converter), NPC (Neutral Point Clamped), NPP (Neutral Point Piloted) and ANPC (Active Neutral Point Clamped).

Claims

1. A multilevel power converter comprising:

n input stages (E<sub>in—

n</sub>), n being at least equal to 1, each input stage having n+1 identical input converters (CONV<sub>x—

En</sub>) that are connected to one another, each converter being supplied with an input voltage (V<sub>x—

En</sub>) and controlled to apply an electrical potential to an output (S<sub>y—

En</sub>) on the basis of said input voltage,

if n is greater than or equal to 2, each input converter of the input stage of rank n−

1 being supplied with the voltage resulting from the electrical potentials applied to two outputs by two converters of rank n,

an output stage (E_out) connected to the input stage of rank 1 and having an output converter (CONV_S) supplied with a differential voltage (V_float) resulting from a first electrical potential applied to the output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to the output of a second input converter of the input stage of rank 1, said output converter being controlled to apply an electrical potential to an output (S<sub>1—

S</sub>), characterized in that;

the input converters (CONV<sub>x—

En</sub>) exhibit an identical topology, chosen from among the architectures of NPC, ANPC, NPP and SMC type,

the output converter (CONV_S) exhibits a different topology than the topology chosen for the input converters, said topology of the output converter being chosen from among a flying capacitor (FC), SMC, NPC, NPP and ANPC architecture.

2. The power converter as claimed in claim 1, characterized in that the input converters (CONV_x—

_En) exhibit a topology of NPP type and in that the output converter (CONV_S) exhibits a flying capacitor topology.

3. The power converter as claimed in claim 1, characterized in that the input converters (CONV_x—

_En) exhibit a topology of NPC type and in that the output converter (CONV_S) exhibits a flying capacitor topology.

4. The power converter as claimed in claim 1, characterized in that the input converters (CONV_x—

_En) exhibit a topology of ANPC type and in that the output converter (CONV_S) exhibits a flying capacitor topology.

5. The power converter as claimed in claim 1, characterized in that the input converters (CONV_x—

_En) exhibit a topology of NPP type and in that the output converter (CONV_S) exhibits a topology of SMC type.

6. The power converter as claimed in claim 1, characterized in that the input converters (CONV_x—

_En) exhibit a topology of NPC type and in that the output converter (CONV_S) exhibits a topology of SMC type.

7. The power converter as claimed in claim 1, characterized in that the input converters (CONV_x—

_En) exhibit a topology of ANPC type and in that the output converter (CONV_S) exhibits a topology of SMC type.