PLL WITH ACROSS-STAGE CONTROLLED DCO

• US 20150311902A1
• Filed: 09/12/2014
• Published: 10/29/2015
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, Tsung-Hsien
• Granted Patent: US 9,369,134 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider

Abstract

In some embodiments, a PLL comprises an across-stage DCO controller and a DCO. The across-stage DCO controller comprises a first detector and a second tuning code adjustor. The first detector receives a first tuning code in a current stage in which an output frequency of the DCO is tuned by a first step size and generates a first detect signal which indicates whether the first tuning code exceeds a first range that the DCO can be correspondingly tuned in the current stage. The second tuning code adjustor adjusts a second tuning code from a previous stage in which the output frequency of the DCO is tuned by a second step size in response to the first detect signal. The second step size is larger than the first step size. The DCO generates the output frequency in response to codes comprising the adjusted second tuning code.

Claims

1. A phase lock loop (PLL), comprising:

an across-stage digital controlled oscillator (DCO) controller comprising;

a first detector configured to receive a first tuning code in a current stage in which an output frequency of a DCO is tuned by a first step size and generate a first detect signal which indicates whether the first tuning code exceeds a first range that the DCO can be correspondingly tuned in the current stage; and

a second tuning code adjustor configured to adjust a second tuning code from a previous stage from which the output frequency of the DCO is tuned by a second step size in response to the first detect signal, the second step size being larger than the first step size; and

the DCO configured to generate the output frequency in response to codes comprising the adjusted second tuning code from the across-stage DCO controller.

2. The PLL of claim 1, wherein the across-stage DCO controller further comprises:

a decoder configured to cause the codes to be thermometer-coded.

3. The PLL of claim 2, wherein the second tuning code adjustor receives the second tuning code which is thermometer-coded and adjust the thermometer-coded second tuning code.

4. The PLL of claim 3, wherein the first detector receives the first tuning code which is binary-coded and generate the first detect signal based on the binary-coded first tuning code.

5. The PLL of claim 1, wherein the across-stage DCO controller further comprises:

a first tuning code compensator configured to adjust the first tuning code such that the output frequency of the DCO is correspondingly compensated when the second tuning code is adjusted.

6. The PLL of claim 1, wherein the across-stage DCO controller further comprises:

a second detector configured to receive the adjusted second tuning code and generate a second detect signal which indicates whether the adjusted second tuning code has reached a bound of a second range that the DCO can be tuned in the previous stage; and

the second tuning code adjustor is further configured to be stopped from adjusting the second tuning code when the second detect signal is asserted.

7. The PLL of claim 6, wherein the across-stage DCO controller further comprises:

a frequency divider configured to divide a reference frequency to generate a frequency divided signal that the second tuning code adjustor is operated under;

the reference frequency is tracked by the output frequency of the DCO; and

the frequency divided signal is stopped when the second detect signal indicates the adjusted second tuning code has reached the bound of the second range.

8. The PLL of claim 6, wherein the second detector consisting essentially of a comparator that operates on unsigned numbers.

9. The PLL of claim 1, wherein the across-stage DCO controller further comprises:

a frequency divider configured to divide a reference frequency to generate a frequency divided signal that the second tuning code adjustor is operated under;

the reference frequency is tracked by the output frequency of the DCO; and

a frequency of the frequency divided signal is less than half a bandwidth of the PLL.

10. The PLL of claim 9, wherein the second tuning code adjustor comprises:

an adjustment selector configured to select one of an increment, a decrement and zero as an adjustment in response to the first detect signal;

an adjustment accumulator configured to accumulate the adjustment in response to the frequency divided signal; and

a summing element configured add the accumulated adjustment from the accumulator to adjust the second tuning code.

11. A phase lock loop (PLL) comprising:

a first detector configured to receive a first tuning code which controls an output frequency of a DCO to be tuned by a first step size and generate a first detect signal which indicates whether the first tuning code exceeds a first range that the first tuning code is allowed to tune the output frequency;

a second tuning code adjustor configured to adjust the second tuning code which controls the output frequency of the DCO to be tuned by a second step size,

the second tuning code being adjusted in response to the first detect signal, and

the second step size being larger than the first step size; and

the DCO configured to generate the output frequency in response to codes comprising the adjusted second tuning code.

12. The PLL of claim 11, further comprising:

a decoder configured to cause the codes to be thermometer-coded.

13. The PLL of claim 12, wherein the second tuning code adjustor receives the second tuning code which is thermometer-coded and adjust the thermometer-coded second tuning code.

14. The PLL of claim 13, wherein the first detector receives the first tuning code which is binary-coded and generate the first detect signal based on the binary-coded first tuning code.

15. The PLL of claim 11, further comprising:

a first tuning code compensator configured to adjust the first tuning code such that the output frequency of the DCO is correspondingly compensated when the second tuning code is adjusted.

16. The PLL of claim 11, further comprising:

a second detector configured to receive the adjusted second tuning code and generate a second detect signal which indicates whether the adjusted second tuning code has reached a bound of a second range that the second tuning code is allowed to tune the output frequency;

the second tuning code adjustor is further configured to be stopped from adjusting the second tuning code when the second detect signal is asserted.

17. The PLL of claim 16, further comprising:

a frequency divider configured to divide a reference frequency to generate a frequency divided signal that the second tuning code adjustor is operated under,

the reference frequency being tracked by the output frequency of the DCO, and

the frequency divided signal being stopped when the second detect signal indicates the adjusted second tuning code has reached the bound of the second range.

18. The PLL of claim 11, further comprising:

a frequency divider configured to divide a reference frequency to generate a frequency divided signal that the second tuning code adjustor is operated under,

the reference frequency being tracked by the output frequency of the DCO, and

a frequency of the divided clock being less than half a bandwidth of the PLL.

19. The PLL of claim 18, wherein the second tuning code adjustor comprises:

an adjustment selector configured to select one of an increment, a decrement and zero as an adjustment in response to the first detect signal;

an adjustment accumulator configured to accumulate the adjustment in response to the frequency divided clock; and

an adder configured to add the accumulated adjustment from the accumulator to adjust the second tuning code.

20. A method, comprising:

receiving, by at least one processor, a first tuning code in a current stage in which an output frequency is tuned by a first step size;

detecting, by the at least one processor, whether the first tuning code exceeds a first range that the output frequency can be correspondingly tuned in the current stage;

adjusting a second tuning code, by the at least one processor, from a previous stage in which the output frequency is tuned by a second step size if the first tuning code exceeds a first range that the output frequency can be correspondingly tuned in the current stage,

the second step size being larger than the first step size.

generating the output frequency in response to codes comprising the adjusted second tuning code.