CONTINUOUS-TIME LINEAR EQUALIZER FOR HIGH-SPEED RECEIVING UNIT

• US 20150312064A1
• Filed: 06/22/2015
• Published: 10/29/2015
• Est. Priority Date: 04/11/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bulzacchelli, John F., Francese, Pier Andrea, Liu, Yong, Toifl, Thomas H.
• Granted Patent: US 9,467,313 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03063 using fractionally spaced delay lines or combinations of fractionally and integrally spaced taps
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Claims

1. A method of operating a continuous-time linear equalizer in a receiving unit of a high-speed data transmission system for receiving an input signal, the method comprising:

providing an equalized output voltage with a signal line; and

operating an active peaking control unit, comprising;

a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail;

a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and

a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

2. The method of claim 1, further comprising coupling, with a gain stage, an input signal to the signal line to provide one of a predetermined or a variable transconductance.

3. The method of claim 2, further comprising coupling a number of serially coupled stages each at least comprising a gain stage and an active peaking control unit, wherein the active peaking control unit is coupled to a different potential of the power supply rail.

4. The method of claim 1, further comprising coupling a further peaking control unit, having a first number of diode-connected transistors, between the signal line and a power supply rail, and a first number of complementary first setting switches each associated with each of the first number of diode-connected transistors to activate a predetermined number of the first number of transistors according to inverted first setting signals ( CN(1 . . . N)), so that the total number of activated active peaking transistors and of the diode-connected transistors corresponds to the first number.

5. The method of claim 1, further comprising coupling a peaking capacitor unit having a predetermined second number of peaking capacitors between the gate-connected terminal of the peaking resistor and the power supply rail, and a second number of second setting switches each associated with each of the second number of peaking capacitors to activate a predetermined number of the second number of peaking capacitors according to second setting signals.

6. The method of claim 1, further comprising coupling a bandwidth control unit having a predetermined third number of load capacitors between the signal line and the power supply rail, and a third number of third setting switches each associated with each of the third number of load capacitors to activate a predetermined number of the third number of load capacitors according to third setting signals.

7. The method of claim 1, further comprising connecting a current source unit, which is configured as a predetermined fourth number of current source transistors, in series with a respective fourth setting switch, wherein a number of the fourth setting switches are configured to be activated in accordance with fourth setting signals to set a gain of the continuous-time linear equalizer.

8. The method of claim 7, wherein the active peaking control unit, the further peaking control unit and the current source unit are configured to reduce the number of activated diode-connected transistors of the further peaking control unit in accordance with the number of activated current source transistors.

9. The method of claim 1, further comprising converting, with a conversion unit, a voltage of the signal line to a current supplied to a summing node, so as to allow a summing up of currents provided by a decision feedback equalizer.

10. The method of claim 9, further comprising configuring a track-and-hold switch to couple the signal line to the conversion unit.

11. The method of claim 9, further comprising configuring an even and odd track-and-hold switch to couple the signal line to two separated conversion units.

12. The method of claim 9, further comprising configuring an even and odd track-and-hold switch to couple the output of the conversion unit to an even and an odd summing node, respectively.

13. The method of claim 1, further comprising:

coupling a common gate stage transistor to one terminal with an input of the continuous-time linear equalizer and to a further terminal with the signal line, wherein a gate terminal of the common gate stage transistor is coupled to one of a predetermined control voltage or an output of a regulation amplifier providing a comparison result between a control voltage and the input signal; and

configuring a current source to supply a predetermined current to the signal line.

14. The method of claim 1, wherein the continuous-time linear equalizer is implemented in a differential configuration and has differential signal lines, wherein the transistors in the one or more units are mirrored.

15. The method of claim 14, further comprising configuring a differential negative impedance unit comprising a fifth number of cross-coupled transistor pairs each comprising two cross-coupled transistors, wherein gate terminals of the cross-coupled transistors are coupled to the respective other differential signal line and wherein the one terminal of each of the cross-coupled transistors is coupled to a respective one of the signal lines and another terminal of each of the cross-coupled transistors is coupled to a respective one of fifth setting switches to activate the respective cross-coupled transistor pair according to fifth setting signals, wherein the further terminals of each pair of the cross-coupled transistors are interconnected with a cross capacity.

16. The method of claim 14, wherein the differential active peaking control unit further comprises a first number of cross-coupling capacitor pairs each including two capacitors each coupling a gate terminal of a respective one of the active peaking transistors of the active peaking transistor pair to a terminal of a respective other of the active peaking transistors of the respective active peaking transistor pair.

17. The method of claim 14, wherein a differential gain stage is formed for coupling the input signals to the respective signal line for providing one of a predetermined or variable transconductance.

18. The method of claim 17, wherein the differential gain stage is formed as a telescopic stage.

19. The method of claim 14, further comprising coupling a differential conversion unit, comprising regenerative cascaded transistor pairs, serially to the respective conversion transistors, with the regenerative cascaded transistor pairs configured with transistors being cross-coupled with respect to the signal lines.

20. The method of claim 1, further comprising configuring a setting unit to provide the respective setting signals according to one of a predetermined setting or minimizing a bit error rate.

21. The method of claim 1, wherein the resistance of the active peaking resistor is chosen so that the frequency where a numerator of a transfer function of the continuous-time linear equalizer is zero, is smaller than the frequency of the poles of a denominator of the transfer function.