Clock and Data Recovery Techniques

• US 20150312078A1
• Filed: 07/06/2015
• Published: 10/29/2015
• Est. Priority Date: 01/10/2009
• Status: Active Grant

• Current Assignee: John W. Bogdan
• Original Assignee: John W. Bogdan
• Inventors: Bogdan, John W.
• Granted Patent: US 9,749,169 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03H 17/0251 Comb filters
• CPC Class Codes: H03H 17/04 Recursive filters
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/22 using more than one loop
• CPC Class Codes: H04L 25/0398 Restoration of channel reciprocity
• CPC Class Codes: H04L 27/2656 Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
• CPC Class Codes: H04L 27/2657 Carrier synchronisation
• CPC Class Codes: H04L 27/2695 with channel estimation, e.g. determination of delay spread, derivative or peak tracking channel estimation H04L25/0202
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Abstract

The Clock and Data Recovery Techniques (CDRT) contribute Inverse Signal Transformation (IST) reversing transmission channel transfer function to achieve a direct recovery of original data from and synchronization of receiver clock to received signals affected by deterministic and random distortions introduced by the channel. The CDRT include also Phase Frequency Recovery Techniques (PFRT) and Direct Synthesis of Receiver Clock (DSRC) presenting feed-forward phase control configurations using an oscillator clock for synthesizing a receiver clock synchronous to a received data carrying signal.

Claims

1. A method for direct synthesis of receiver clock (DSRC) using an oscillator clock for producing a synthesized clock synchronous to a referencing frame providing frequency and phase transmittal from a frame of a received orthogonal frequency division multiplexing (OFDM) signal, wherein a clock synthesis configuration comprises a phase detector measuring phase errors between the referencing frame and a corresponding frame of the oscillator clock, a programmable control unit (PCU) reading the measured phase errors in order to produce phase amendments, a phase synthesizer applying the phase amendments to the oscillator clock in order to produce the synthesized clock specified by the phase amendments without introducing uncontrolled phase transients;

wherein the DSRC method comprises the steps of;

processing the received OFDM signal in frequency domain in order to recover selected tones from the received OFDM signal,

using the recovered selected tones for detecting boundaries of the frame of the received OFDM signal,

using the boundary detections for defining the referencing frame;

using the phase detector for the measuring the phase errors between the referencing frame and the corresponding frame of the oscillator clock;

using, by the PCU, preceding measured phase errors for calculating predicted phase amendments designed to compensate the measured phase errors;

using, by the PCU, the measured phase errors and the predicted phase amendments for calculating phase tracking errors between a frame of the synthesized clock and the referencing frame;

using, by the PCU, the phase tracking errors and following said predicted phase amendments for calculating following said phase amendments designed to minimize following said phase tracking errors;

applying, by the phase synthesizer, the following phase amendments to the oscillator clock in order to minimize the phase tracking errors.

2. A method for direct synthesis of receiver clock (DSRC) using an oscillator clock for producing a synthesized clock synchronous to a referencing frame providing frequency and phase transmittal from a frame of a received orthogonal frequency division multiplexing (OFDM) signal, wherein a clock synthesis configuration comprises a phase detector measuring phase errors between the referencing frame and a corresponding frame of the oscillator clock, a programmable control unit (PCU) reading the measured phase errors in order to produce phase amendments, a phase synthesizer applying the phase amendments to the oscillator clock in order to produce the synthesized clock specified by the phase amendments without introducing uncontrolled phase transients;

wherein the DSRC method comprises the steps of;

detecting boundaries of the frame of the received OFDM signal by processing the received OFDM signal or a sub-carrier signal recovered from the received OFDM signal;

wherein a known detection delay occurs between receptions of the boundaries of the frame of the received OFDM signal and the detections of the boundaries of the frame of the received OFDM signal;

using the boundary detections for defining the referencing frame;

using the phase detector for the measuring the phase errors between the referencing frame and the corresponding frame of the oscillator clock;

using, by the PCU, preceding measured phase errors for calculating predicted phase amendments designed to compensate the measured phase errors;

using, by the PCU, the measured phase errors and the predicted phase amendments for calculating phase tracking errors between a frame of the synthesized clock and the referencing frame;

using, by the PCU, the phase tracking errors and following said predicted phase amendments for calculating following said phase amendments designed to minimize following said phase tracking errors;

applying, by the phase synthesizer, the following phase amendments to the oscillator clock in order to minimize the phase tracking errors.

3. A method for direct synthesis of receiver clock (DSRC) using an oscillator clock for producing a synthesized clock synchronous to a referencing frame providing frequency and phase transmittal from a frame of a received orthogonal frequency division multiplexing (OFDM) signal, wherein a clock synthesis configuration comprises a phase detector measuring phase errors between the referencing frame and a corresponding frame of the oscillator clock, a programmable control unit (PCU) reading the measured phase errors in order to produce phase amendments, a phase synthesizer applying the phase amendments to the oscillator clock in order to produce the synthesized clock specified by the phase amendments without introducing uncontrolled phase transients;

wherein the DSRC method comprises the steps of;

the measuring the phase errors by estimating lengths differences between periods of the referencing frame and corresponding nominal periods of the frame of the oscillator clock;

wherein each of the nominal periods is defined by a number of such oscillator clocks expected to occur during a corresponding period of the referencing frame when the oscillator clock has a predefined frequency relation to the frame of the OFDM signal;

using, by the PCU, preceding the measured phase errors for calculating predicted phase amendments designed to compensate pro-actively the measured phase errors;

using, by the PCU, the measured phase errors and the predicted phase amendments for calculating phase tracking errors between a frame of the synthesized clock and the referencing frame;

using, by the PCU, the phase tracking errors and following said predicted phase amendments for calculating following said phase amendments designed to minimize following said phase tracking errors;

applying, by the phase synthesizer, the following phase amendments to the oscillator clock in order to minimize the phase tracking errors.