TABLE FETCH PROCESSOR INSTRUCTION USING TABLE NUMBER TO BASE ADDRESS TRANSLATION

• US 20150317163A1
• Filed: 05/01/2014
• Published: 11/05/2015
• Est. Priority Date: 05/01/2014
• Status: Active Grant

• Current Assignee: Netronome Systems Incorporated
• Original Assignee: Netronome Systems Incorporated
• Inventors: Stark, Gavin J.
• Granted Patent: US 10,853,074 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.

Claims

1. A method comprising:

(a) receiving an input value onto a processor;

(b) converting the input value into a base address value and an offset value, wherein the base address is the base address of a table of code in an external memory, and wherein the offset value indicates an offset from the base address to a section of code within the table;

(c) in response to the receiving of the input value of (a) fetching a first block of information of the section of code without use by the processor of any instruction counter, wherein the first block of information includes a plurality of instructions, wherein at least one of the instructions of the first block is a fetch instruction, and wherein the processor only fetches instructions in response to receiving an input value from an external source or as a result of executing a fetch instruction; and

(d) executing the instructions of the first block of information including executing the fetch instruction.

2. The method of claim 1, wherein the processor has a pipeline, wherein the pipeline prior to the receiving of (a) is not being clocked, and wherein the receiving of the input value in (a) causes a clocking of the pipeline to start.

3. The method of claim 1, wherein the processor has a pipeline, and method further comprising:

(e) executing a finished instruction, wherein execution of the finished instruction causes a clocking of the pipeline to stop.

4. The method of claim 1, wherein the input value is an input data value received onto an input data value port of the processor.

5. The method of claim 1, wherein the input value is a fetch information value received onto an initial fetch information port of the processor.

6. The method of claim 1, wherein the processor has a pipeline, wherein the pipeline comprises a fetch request stage, and wherein a lookup table circuit in the fetch request stage determines the base address value from a part of the input value.

7. The method of claim 1, wherein the external memory has a lookup table circuit, wherein a memory request received onto the external memory includes a table number value, and wherein the lookup table circuit generates the base address value from the table number value.

8. The method of claim 1, wherein the processor has a pipeline, wherein the pipeline comprises a fetch request stage, wherein the input value includes a table number, and wherein a lookup table circuit in the fetch request stage determines the base address value from the table number.

9. The method of claim 1, wherein the input value is a part of a network packet.

10. The method of claim 1, wherein the input value is a set of flags that characterize a network packet.

11. The method of claim 1, wherein the processor includes a pipeline, wherein the converter of (b) is performed by a fetch stage of the pipeline.

12. A processor comprising:

means for fetching blocks of information from a memory system external to the processor without the use of an instruction counter, wherein the means only fetches blocks of information from the memory system in response to either a receiving of a fetch information value onto the processor from an external source or to a receiving of a fetch information value from a stage within the processor, wherein the processor includes no instruction counter and the means fetches block of information without use of any instruction counter, wherein a fetch information value received onto the processor from the external source includes a table number value, and wherein the means determines a base address value from the table number value, and wherein the means includes the base address value in a memory request that is supplied from the means to the memory system, wherein the base address is a base address of a table that contains the block of information;

a decode stage coupled to the means, wherein the decode stage can decode a fetch instruction;

a register file read stage coupled to the decode stage; and

an execute stage coupled to the register file read stage, wherein the execute stage executes the fetch instruction by outputting fetch information to the fetch request stage thereby prompting the means to fetch a block of information.

13. The processor of claim 12, wherein the means for fetching comprises a fetch request stage and a fetch shift selector stage, wherein the fetch request stage includes a lookup table circuit and outputs memory requests to the memory system, and wherein the fetch request selector stage receives memory responses from the memory system.

14. The processor of claim 12, wherein the memory request includes an offset value, and wherein the means is also for determining the offset value and then including the offset value in the memory request.

15. The processor of claim 14, wherein the offset value is a part of the fetch information value.

16. The processor of claim 14, wherein an input data value is received onto the processor along with the fetch information value, and wherein the offset value is a part of the input data value.

17. The processor of claim 12, wherein the fetch information value is a fetch instruction.

18. A system comprising:

a processor comprising;

means for fetching blocks of information without the use of an instruction counter, wherein the means only fetches blocks of information in response to either a receiving of a fetch information value onto the processor from an external source or to a receiving of a fetch information value from a stage within the processor, wherein the processor includes no instruction counter and the means fetches blocks of information without use of any instruction counter, wherein a fetch information value received onto the processor from the external source includes a table number value;

a decode stage coupled to the means, wherein the decode stage can decode a fetch instruction;

a register file read stage coupled to the decode stage; and

an execute stage coupled to the register file read stage, wherein the execute stage executes the fetch instruction by outputting fetch information to the fetch request stage thereby prompting the means to fetch a block of information; and

a memory system external to the processor, wherein the memory system receives a memory request from the processor, wherein the memory request includes the table number value, wherein the memory system determines a base address value from the table number value, and wherein the base address value is a base address of a table of code stored in the memory system that contains the block of information.

19. The system of claim 18, wherein a fetch information value received onto the processor from the external source includes a flag value, and wherein the memory system uses the flag value from the fetch information value to determine an offset value, and wherein the block of information is stored in the memory system at an address given by the sum of the base address value and the offset value.

20. The processor of claim 18, wherein the means for fetching comprises a fetch request stage and a fetch shift selector stage, wherein the fetch request stage outputs memory requests to the memory system, and wherein the fetch request selector stage receives memory responses from the memory system.