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COMPUTER ARCHITECTURE HAVING SELECTABLE, PARALLEL AND SERIAL COMMUNICATION CHANNELS BETWEEN PROCESSORS AND MEMORY

  • US 20150317277A1
  • Filed: 05/01/2014
  • Published: 11/05/2015
  • Est. Priority Date: 05/01/2014
  • Status: Active Grant
First Claim
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1. An electronic computer comprising:

  • a processor system having;

    (a) a first latency-sensitive processor executing a general instruction set for general purpose computation;

    (b) a second latency-insensitive processor executing a specialized instruction set for specialized computation, wherein the latency-insensitive processor is less sensitive to latency in access to electronic memory than the latency-sensitive processor;

    an electronic memory communicating with the processor system and storing data words for reading and writing by the processor system;

    a parallel bus communicating between the processor system and the memory providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane;

    a serial bus communicating between the processor system and the memory providing transmission of different bits of given data words serially on at least one conductor of a serial lane; and

    a memory access manager preferentially routing memory access by the latency-sensitive processor through the parallel bus and memory access by the latency-insensitive processor through the serial bus.

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