Integrated Circuits with Asymmetric and Stacked Transistors

• US 20150318029A1
• Filed: 05/02/2014
• Published: 11/05/2015
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Liu, Jun, Xu, Yanzhong, Sinha, Shankar, Lee, Shih-Lin S., Tung, Jeffrey Xiaoqi, Ratnakumar, Albert, Xiang, Qi, Rahim, Irfan, Lee, Andy L., Watt, Jeffrey T., Perisetty, Srinivas
• Granted Patent: US 9,496,268 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Claims

1. An integrated circuit, comprising:

an array of memory cells loaded with respective data bits, each memory cell having an output at which a static output signal is produced based on the data bit loaded into that memory cell; and

programmable circuitry including a plurality of programmable transistors, each programmable transistor having a gate that is electrically connected to a respective one of the outputs to receive a respective one of the static output signals, wherein the memory cells each include at least one asymmetric transistor that exhibits a strong mode of operation and a weak mode of operation.

2. The integrated circuit defined in claim 1 wherein the asymmetric transistor of each memory cell comprises an address transistor having first and second source-drains of a first doping type and having an energy-barrier-inducing implant at the second source drain, wherein the energy-barrier-inducing implant has a second doping type opposite to the first doping type.

3. The integrated circuit defined in claim 2 wherein the first doping type comprises n-type and wherein the second doping type comprises p-type.

4. The integrated circuit defined in claim 1 wherein the memory cells each include at least one stacked transistor.

5. The integrated circuit defined in claim 1 wherein each of the memory cells includes two inverters, wherein each of the inverters has a p-channel transistor connected in series with a pair of n-channel transistors, and wherein each pair of n-channel transistors includes first and second series-connected n-channel transistors with different threshold voltages.

6. The integrated circuit defined in claim 1 wherein each of the memory cells includes a bistable element formed from four interconnected inverter-like circuits.

7. The integrated circuit defined in claim 6 wherein each inverter-like circuit includes a p-channel transistor and an n-channel transistor connected in series.

8. The integrated circuit defined in claim 1 wherein each of the memory cells includes a bistable element having at least eight transistors.