SPACER TO PREVENT SOURCE-DRAIN CONTACT ENCROACHMENT

• US 20150318204A1
• Filed: 04/30/2014
• Published: 11/05/2015
• Est. Priority Date: 04/30/2014
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Peng, Wen-Pin, Lee, Yong M., Hu, Yue
• Granted Patent: US 9,385,030 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be etched partway to a source-drain region of the semiconductor device. A dielectric liner can be deposited in this trench. A second etch can be performed on the lined trench to etch the contact trench channel the remainder of the way to the source-drain region. This leaves a portion of the dielectric liner remaining in the trench (e.g., covering the vertical walls of the trench) after the second etch.

Claims

1. A method for preventing contact encroachment in a semiconductor device, comprising:

etching a first portion of a contact trench to a source-drain region of the semiconductor device;

depositing a dielectric liner in the trench; and

etching a remainder of the contact trench channel to the source-drain region,

wherein at least a portion of the dielectric liner deposited on horizontal walls of the trench remains after the remainder of the contact trench has been formed.

2. The method of claim 1, wherein the etching of the first portion of the contact trench further includes:

forming a hardmask layer over the semiconductor device, the hardmask layer having an opening over the source-drain region; and

etching the first portion of the contact trench to a depth that is lower than a susceptible region for a potential defect,

wherein the portion of the dielectric liner that remains covers the potential defect region.

3. The method of claim 2, wherein the dielectric liner comprises a substance that is resistant to a substance used to strip the hardmask layer.

4. The method of claim 3, wherein the hardmask layer comprises titanium nitride.

5. The method of claim 4, wherein the substance is selected from a group consisting of:

silicon carbon oxide, silicon nitride, or silicon oxide.

6. The method of claim 2,

wherein the susceptible region is located at a junction of an inter-layer dielectric layer and an adjoining stress nitride encapsulation layer, and

wherein the potential defect is selected from a group, consisting of:

a residue of material from formation of a metal gate or an interface flaw between the inter-layer dielectric layer and the adjoining stress nitride encapsulation layer.

7. The method of claim 6, wherein the metal gate is a replacement metal gate in a replacement metal gate transistor.

8. The method of claim 1, further comprising forming a contact to the source-drain region in the contact trench.

9. A method for forming a semiconductor device, comprising:

forming a source-drain region, a replacement metal gate, and an inter-layer dielectric layer on a substrate;

forming a stress nitride encapsulation layer over the replacement metal gate and the inter-layer dielectric layer;

detecting a susceptible region for a potential defect in the semiconductor device between the metal gate and the source-drain region;

etching a first portion of a contact trench to a source-drain region of the semiconductor device, the first portion of the contact trench extending to a depth that is below the susceptible region and above the source-drain region;

depositing a dielectric liner in the trench, wherein a portion of the dielectric liner overlays the susceptible region; and

etching a remainder of the contact trench channel to the source-drain region while leaving the portion of the dielectric liner that overlays the susceptible region.

10. The method of claim 9, further comprising:

forming a hardmask layer for the etching of the first and second portions of the contact trench over the stress nitride encapsulation layer; and

removing the hardmask layer using a chemical hardmask strip process,

wherein the portion of the dielectric liner that overlays the susceptible region prevents the chemicals used in the chemical hardmask strip process from reaching the susceptible region.

11. The method of claim 10, wherein the hardmask layer comprises titanium nitride.

12. The method of claim 10, wherein the dielectric liner comprises a composition selected from a group, consisting of:

silicon carbon oxide, silicon nitride, or silicon oxide.

13. The method of claim 10, wherein the susceptible region is located at a junction of the inter-layer dielectric layer and the stress nitride encapsulation layer.

14. The method of claim 13, wherein the potential defect is caused by a residue of material from formation of the metal gate left in the susceptible region by an incomplete planarization of the metal gate.

15. The method of claim 13, wherein the potential defect is caused by an interface flaw between the inter-layer dielectric layer and the adjoining stress nitride encapsulation layer.

16. The method of claim 9, wherein the metal gate is a replacement metal gate in a replacement metal gate transistor.

17. The method of claim 9, further comprising forming a contact to the source-drain region in the contact trench.

18. A semiconductor device, formed via a process, comprising:

forming a source-drain region, a replacement metal gate, and an inter-layer dielectric layer on a substrate;

forming a stress nitride encapsulation layer over the replacement metal gate and the inter-layer dielectric layer;

detecting a susceptible region for a potential defect in the semiconductor device between the metal gate and the source-drain region;

etching a first portion of a contact trench to a source-drain region of the semiconductor device, the first portion of the contact trench extending to a depth that is below the susceptible region and above the source-drain region;

depositing a dielectric liner in the trench, wherein a portion of the dielectric liner overlays the susceptible region; and

etching a remainder of the contact trench channel to the source-drain region while leaving the portion of the dielectric liner that overlays the susceptible region.

19. The semiconductor device of claim 18, further comprising:

forming a hardmask layer for the etching of the first and second portions of the contact trench over the stress nitride encapsulation layer; and

removing the hardmask layer using a chemical hardmask strip process,

wherein the portion of the dielectric liner that overlays the susceptible region prevents the chemicals used in the chemical hardmask strip process from reaching the susceptible region.

20. The method of claim 19,

wherein the hardmask layer comprises titanium nitride, and

wherein the dielectric liner comprises a composition selected from a group, consisting of:

silicon carbon oxide, silicon nitride, or silicon oxide.