SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20150318301A1
• Filed: 05/01/2015
• Published: 11/05/2015
• Est. Priority Date: 05/02/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Joonhee, Park, Jintaek
• Granted Patent: US 9,530,789 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Semiconductor memory devices and methods of fabricating the same are provided. A semiconductor memory device includes stack gate structures that are spaced apart from each other in a first direction horizontal to a substrate. Each of the stack gate structures includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. Vertical channel structures penetrate the stack gate structures. A source plug line is provided between the stack gate structures. The source plug line is in contact with the substrate and extends in a second direction intersecting the first direction. The substrate being in contact with the source plug line includes a plurality of protruding regions formed along the second direction. Each of the protruding regions has a first width, and the protruding regions are spaced apart from each other by a first distance greater than the first width.

Claims

1. A semiconductor memory device comprising:

a substrate;

a plurality of stack gate structures spaced apart from each other in a first direction parallel to a main surface of the substrate, each of the stack gate structures including insulating layers and gate electrodes that are alternately and repeatedly stacked on the substrate;

a plurality of vertical channel structures penetrating each of the stack gate structures; and

a source plug line disposed between the stack gate structures, the source plug line being in contact with the substrate and extending in a second direction intersecting the first direction,

wherein the substrate being in contact with the source plug line includes a plurality of protruding regions arranged along the second direction,

wherein each of the protruding regions has a first width, and

wherein the protruding regions are spaced apart from each other by a first distance greater than the first width.

2. The semiconductor memory device of claim 1, wherein each of the vertical channel structures comprises:

a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a vertical channel pattern including a semiconductor material.

3. The semiconductor memory device of claim 2, wherein the vertical channel pattern includes a first vertical channel pattern vertically protruded from the substrate and a second vertical channel pattern vertically disposed on the first vertical channel pattern, and

wherein the tunnel dielectric layer, the charge storage layer and the blocking dielectric layer are disposed between the second vertical channel pattern and the plurality of stack gate structures.

4. The semiconductor memory device of claim 2, wherein the source plug line includes a barrier layer and a conductive layer on the barrier layer.

5. The semiconductor memory device of claim 1, further comprising:

an isolation insulating pattern disposed between the source plug line and the stack gate structures.

6. The semiconductor memory device of claim 5, further comprising:

a lower isolation insulating pattern selectively disposed on the plurality of protruding regions,

wherein the lower isolation insulating pattern is in direct contact with a bottom surface of the source plug line, and

wherein the lower isolation insulating pattern is connected to the isolation insulating pattern.

7. The semiconductor memory device of claim 6, further comprising:

a supporting pattern disposed on the stack gate structures,

wherein the supporting pattern comprises;

a plurality of bridges crossing over the source plug line in the first direction and spaced apart from each other in the second direction; and

fixing portions connected to the bridges and disposed on the stack gate structures, respectively.

8. The semiconductor memory device of claim 7, wherein the bridges are arranged in a zigzag form along the first direction.

9. The semiconductor memory device of claim 7, wherein each of the bridges substantially vertically overlaps with each of the protruding regions.

10. The semiconductor memory device of claim 7, wherein the supporting pattern has a linear type extending in the first direction.

11. The semiconductor memory device of claim 1, wherein the source plug line comprises an upper portion including a plurality of groove regions arranged along the second direction.

12. The semiconductor memory device of claim 1, further comprising:

a common source region in contact with the source plug line and disposed in the substrate

13. A semiconductor memory device comprising:

a plurality of stack gate structures disposed on a substrate, each of the stack gate structures including insulating layers and gate electrodes that are alternately and repeatedly stacked on the substrate, and the stack gate structures being spaced apart from each other in a first direction;

a plurality of vertical channel structures penetrating each of the stack gate structures;

a source plug line disposed between the plurality of stack gate structures, the source plug line including a conductive material and extending in a second direction intersecting the first direction; and

a common source region being in contact with the source plug line and disposed in the substrate,

wherein the common source region comprises a first dopant region and a second dopant region that are alternately formed along the second direction,

wherein the first dopant region has a first height and the second dopant region has a second height, and

wherein the first height is greater than the second height.

14. The semiconductor memory device of claim 13, further comprising:

a third dopant region disposed in the second dopant region,

wherein a dopant concentration of the third dopant region is higher than those of the first and second dopant regions.

15. The semiconductor memory device of claim 14, further comprising:

a lower isolation insulating pattern disposed on the first dopant region.

16. The semiconductor memory device of claim 15, further comprising:

an isolation insulating pattern disposed between the source plug line and the stack gate structures,

wherein the isolation insulating pattern is connected to the lower isolation insulating pattern.

17. The semiconductor memory device of claim 13, further comprising:

a supporting pattern disposed on the stack gate structures,

wherein the supporting pattern comprises;

a plurality of bridges crossing over the source plug line in the first direction and spaced apart from each other in the second direction; and

fixing portions connected to the bridges and disposed on the stack gate structures, respectively.

18. A semiconductor memory device comprising:

a plurality of vertical channel structures disposed on a substrate and extending in a direction vertical to the substrate;

a plurality of stack gate structures surrounding the vertical channel structures and including gate electrodes stacked in the direction vertical to the substrate, the stack gate structures being spaced apart from each other in a first direction parallel to the substrate; and

a common source region formed in the substrate and including a plurality of protruding regions that are formed along a second direction intersecting the first direction between the stack gate structures,

wherein each of the protruding regions has a first width in the second direction, and

wherein the protruding regions are spaced apart from each other by a first distance greater than the first width.

19. The semiconductor memory device of claim 18, further comprising

a source plug line disposed on the common source region, the source plug line being in contact with the common source region and extending in the second direction.

20. The semiconductor memory device of claim 18, further comprising:

a supporting pattern disposed on the stack gate structures,

wherein the supporting pattern comprises;

a plurality of bridges crossing over the source plug line in the first direction and spaced apart from each other in the second direction; and

fixing portions connected to the bridges and disposed on the stack gate structures, respectively.

21-37. -37. (canceled)