SEMICONDUCTOR DEVICE WITH VOLTAGE-SUSTAINING REGION CONSTRUCTED BY SEMICONDUCTOR AND INSULATOR CONTAINING CONDUCTIVE REGIONS

• US 20150318346A1
• Filed: 07/10/2015
• Published: 11/05/2015
• Est. Priority Date: 11/30/2011
• Status: Abandoned Application

• Current Assignee: University of Electronic Science and Technology of China
• Original Assignee: Xingbi Chen
• Inventors: CHEN, XINGBI
• Application Number:
  US14/796,206
• Publication Number:
  US 20150318346A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7424 having a built-in localised breakdown/breakover region, e.g. self-protected against destructive spontaneous, e.g. voltage breakover, firing
• CPC Class Codes: H01L 29/7432 Asymmetrical thyristors with a particular shorted anode structure H01L29/0834
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device has at least a cell between two opposite main surfaces. Each cell has a first device feature region contacted with the first main surface and a second device feature region contacted with the second main surface. There is a voltage-sustaining region between the first device feature region and the second device feature region, which includes at least a semiconductor region and an insulator region containing conductive region(s). The semiconductor region and the insulator region contact directly with each other. The structure of such voltage-sustaining region can not only be used to implement high-voltage devices, but further be used as a junction edge technique of high-voltage devices.

Claims

1. A semiconductor device, comprising a first main surface and a second main surface opposite to said first main surface, wherein at least a cell is located between said first main surface and said second main surface, wherein said cell has a first device feature region contacted with said first main surface and a second device feature region contacted with said second main surface;

wherein a voltage-sustaining region is located between said first device feature region and said second device feature region, wherein said voltage-sustaining region includes at least a semiconductor region and an insulator region having at least a conductive region inside, said insulator region having at least a conductive region is called as (I+C)-region;

wherein said semiconductor region and said (I+C)-region contact directly each other;

said semiconductor device comprising at least two electrodes, wherein one electrode is contacted directly with a portion or the total of said first main surface, another electrode is contacted directly with a portion or the total of said second main surface, and said two electrodes are located outside of the region between said first main surface and said second main surface.

2. The semiconductor device according to claim 1, comprising a plurality of close-packed cells, wherein in a cross section between said first device feature region and said second device feature region, the cross section structure of said voltage-sustaining region is interdigitated pattern, or hexagonal pattern, or rectangular pattern, or square pattern, or mosaic square pattern;

wherein the ratio of the cross sectional area of said (I+C)-region(s) to the cross sectional area of said semiconductor region keeps constant or varies at different distances to said first main surface.

3. The semiconductor device according to claim 1, wherein said semiconductor region of said voltage-sustaining region includes a semiconductor region of a first conductivity type and/or a semiconductor region of a second conductivity type.

4. The semiconductor device according to claim 1, wherein said second device feature region is a semiconductor region of a first conductivity type;

wherein said first device feature region includes a semiconductor region of a second conductivity type contacted directly with said semiconductor region of said voltage-sustaining region, and/or further includes a semiconductor region of said second conductivity type or a conductor being contacted directly with said (I+C)-region(s) of said voltage-sustaining region.

5. The semiconductor device according to claim 1, wherein said second device feature region has a semiconductor region of a second conductivity type being contacted directly with said second main surface and a semiconductor region of a first conductivity type being contacted directly with said semiconductor region of said second conductivity type;

wherein said semiconductor region of said first conductivity type is further contacted with said voltage-sustaining region;

wherein said first device feature region includes a semiconductor region of said second conductivity type contacted directly with said semiconductor region of said first conductivity type of said voltage-sustaining region and/or further includes a semiconductor region of said second conductivity type or a conductor being contacted directly with said (I+C)-region(s) of said voltage-sustaining region.

6. The semiconductor device according to claim 1, wherein said semiconductor device is a Schottky diode, said second device feature region is a semiconductor region of a first conductivity type;

wherein said first device feature region is made of metal being contacted directly with a semiconductor region of said first conductivity type of said voltage-sustaining region;

wherein said first device feature region and said second device feature region are contacted with two conductors respectively serving as two electrodes of said Schottky diode;

and wherein said first device feature region further has a semiconductor region of a second conductivity type or a conductor being contacted directly with said (I+C)-region(s) of said voltage-sustaining region.

7. The semiconductor device according to claim 1, said semiconductor device being a Junction Barrier Controlled Schottky (JBS) rectifier or a Merged P-i-N/Schottky (MPS) rectifier, wherein said second device feature region is a semiconductor region of a first conductivity type;

wherein said first device feature region includes a metal region being contacted directly with a semiconductor region of said first conductivity type of said voltage-sustaining region;

wherein said first device feature region further includes a semiconductor region of a second conductivity type being contacted directly with semiconductor region of said first conductivity type of said voltage-sustaining region and said metal region;

and wherein said first device feature region and said second device feature region are contacted with two conductors respectively serving as two electrodes of said JBS rectifier or said MPS rectifier.

8. The semiconductor device according to claim 4, said semiconductor device being a Bipolar Junction Transistor (BJT), wherein said second device feature region is a semiconductor region of said first conductivity type;

wherein said voltage-sustaining region has at least a semiconductor region of said first conductivity type serving as a collector region of said BJT;

wherein said semiconductor region of said second conductivity type of said first device feature region serves as a base region of said BJT;

wherein said first device feature region further includes a semiconductor region of said first conductivity type surrounded by said base region except the part on said first main surface, serving as an emitter region of said BJT;

and wherein a conductor covering on said semiconductor region of said first conductivity type of said second device feature region serves as a collector electrode, a conductor covering on said base region serves as a base electrode and a conductor covering on said emitter region serves as an emitter electrode.

9. The semiconductor device of claim 4, wherein said semiconductor device is a Insulator Gate Field Effect Transistor (IGFET), wherein said second device feature region is a semiconductor region of said first conductivity type, serving as drain region of said IGFET;

wherein said voltage-sustaining region has at least a semiconductor region of said first conductivity type serving as a drift region of said IGFET;

wherein said semiconductor region of said second conductivity type of said first device feature region serves as a source-body region of said IGFET;

wherein said first device feature region further includes a semiconductor region of said first conductivity type surrounded by said source-body region except the part on said first main surface, serving as a source region of said IGFET;

wherein an insulator layer covers on said first main surface started from a part of said source region, across an area of said source-body region, ended at a part of said semiconductor region of said first conductivity type of said voltage-sustaining region, serving as a gate insulator of said IGFET;

and wherein a conductor covering on said drain region serves as a drain electrode, a conductor contacted with both said source-body region and said source region serves as a source electrode and a conductor covering on said gate insulator serves as a gate electrode.

10. The semiconductor device of claim 5, wherein said semiconductor device is an Insulator Gate Bipolar Transistor (IGBT), wherein said semiconductor region of said second conductivity type of said second device feature region is an anode region of said IGBT;

wherein said semiconductor region of said second conductivity type of said first device feature region serves as a source-body region of IGFET in said IGBT;

wherein said first device feature region further includes a semiconductor region of said first conductivity type surrounded by said source-body region except the part on said first main surface, serving as a source region of said IGFET in said IGBT;

wherein an insulator layer covers on said first main surface starting from a part of said source region, across an area of said source-body region, ended at a part of said semiconductor region of said first conductivity type of said voltage-sustaining region, serving as a gate insulator of said IGFET in said IGBT;

and wherein a conductor covering on said anode region serves as an anode electrode, a conductor contacted with both said source-body region and said source region serves as a cathode electrode and a conductor covering on said gate insulator serves as a gate electrode.

11. The semiconductor device of claim 5, wherein said semiconductor device is a thyristor, wherein said semiconductor region of said second conductivity type in said second device feature region is an anode region of said thyristor;

wherein said semiconductor region of said second conductivity type of said first device feature region serves as a gate region of said thyristor;

wherein said first device feature region further includes a semiconductor region of said first conductivity type surrounded by said gate region except the part on said first main surface, serving as a cathode region of said thyristor;

wherein a conductor covering on a part of said gate region and said (I+C)-region(s) of said voltage-sustaining region serves as a gate electrode of said thyristor;

and wherein a conductor covering on said anode region serves as an anode electrode and a conductor covering on said cathode region serves as a cathode electrode.

12. The semiconductor device according to claim 1, wherein at least a cell of said semiconductor device is located at an edge of an operation region of a semiconductor device, serving as a junction edge technique for sustaining voltage;

and wherein said (I+C)-region(s) of said voltage-sustaining region is contacted with a semiconductor region of a second conductivity type of said first device feature region through a semiconductor region of said second conductivity type or a conductor.

13. The semiconductor device according to claim 1, wherein inside said (I+C)-region, there is at least a conductive region of strip-type.

14. The semiconductor device according to claim 1, wherein inside said (I+C)-region, there is at least a conductive region of rectangular-type.

15. The semiconductor device according to claim 1, wherein inside said (I+C)-region, there is at least a conductive region of U-shape.

16. The semiconductor device according to claim 1, wherein inside said (I+C)-region, there is at least a conductive region of granular.