Thermal Shunt

• US 20150318665A1
• Filed: 06/17/2015
• Published: 11/05/2015
• Est. Priority Date: 02/28/2014
• Status: Abandoned Application

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Liang, Di
• Application Number:
  US14/742,279
• Publication Number:
  US 20150318665A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01S 5/021 Silicon based substrates
• CPC Class Codes: H01S 5/02461 Structure or details of the laser chip to manipulate the heat flow, e.g. passive layers in the chip with a low heat conductivity
• CPC Class Codes: H01S 5/02469 Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC
• CPC Class Codes: H01S 5/1071 Ring-lasers
• CPC Class Codes: H01S 5/4012 Beam combining, e.g. by the use of fibres, gratings, polarisers, prisms
• CPC Class Codes: H01S 5/4087 emitting more than one wavelength

Abstract

A thermal shunt is to transfer heat from a sidewall of a device to a silicon substrate. The device is associated with a Silicon-On-Insulator (SOI) including a buried oxide layer. The thermal shunt extends through the buried oxide layer to the silicon substrate.

Claims

1. A device, comprising:

a component disposed on a silicon device layer of a Silicon-On-Insulator (SOI), wherein the SOI includes a buried oxide layer sandwiched between the silicon device layer and a silicon substrate; and

a thermal shunt to contact a part of the device and extend through the silicon device layer and buried oxide layer to the silicon substrate to transfer heat from the device to the silicon substrate.

2. The device of claim 1, wherein the thermal shunt is composed of a dielectric to contact the part of the device for surface dangling bond passivation.

3. The device of claim 1, wherein the thermal shunt is electrically insulating.

4. The device of claim 1, further comprising a thermal substrate shunt, laterally displaced from the thermal shunt, to extend through the buried oxide layer to transfer heat from the silicon device layer through the buried oxide layer to the silicon substrate.

5. The device of claim 4, wherein a top surface of the thermal substrate shunt is offset below a top surface of the silicon device layer.

6. An optical interconnect comprising:

a photon generator bonded to a silicon device layer of a Silicon-On-Insulator (SOI) to resonate optical modes;

a buried oxide layer sandwiched between the silicon device layer and a silicon substrate; and

a thermal shunt to extend from the photon generator through the silicon device layer and the buried oxide layer to the silicon substrate, wherein the thermal shunt is proximate to a part of the photon generator to transfer heat from the part and substantially confine the resonated optical modes within the photon generator.

7. The optical interconnect of claim 6, wherein the thermal shunt is thermally conductive and associated with an optical loss characteristic to substantially confine the resonated optical modes within the photon generator.

8. The optical interconnect of claim 6, wherein the thermal shunt is diamond.

9. The optical interconnect of claim 6, wherein the thermal shunt is aluminum oxide.

10. The optical interconnect of claim 6, further comprising a waveguide to resonate optical modes.

11. A method of transferring heat from a Silicon-On-Insulator (SOI) device, comprising:

passivating, using a thermal shunt material, a part of the device disposed on a silicon device layer of a Silicon-On-Insulator (SOI); and

extending the thermal shunt material through the silicon device layer and a buried oxide layer of the SOI to a silicon substrate of the SOI, to transfer heat from the part of the device to the silicon substrate.

12. The method of claim 11, further comprising generating photons using the device.

13. The method of claim 11, further comprising electrically insulating the part of the device using the thermal shunt material.

14. The method of claim 11, further comprising extending a thermal substrate shunt through the silicon device layer and the buried oxide layer to transfer heat from the silicon device layer through the buried oxide layer to the silicon substrate.

15. The method of claim 13, further comprising laterally offsetting the thermal substrate shunt relative to the part to attenuate higher order modes of the device.