HYBRID MEMORY CUBE SYSTEM INTERCONNECT DIRECTORY-BASED CACHE COHERENCE METHODOLOGY

• US 20150324290A1
• Filed: 05/07/2015
• Published: 11/12/2015
• Est. Priority Date: 05/08/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Murphy, Richard C., Leidel, John
• Granted Patent: US 10,838,865 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2212/622 State-only directory, i.e. not recording identity of sharing or owning nodes
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.

Claims

1. A computing system comprising:

a plurality of host processors; and

a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors, an HMC device including;

a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and

a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.

2. The system of claim 1, wherein memory of the memory die is mapped as shared memory for a computing system and the logic circuitry of an HMC device is configured to manage the communication of information between the host processors and the shared memory using an input/output (I/O) protocol, and implement the memory coherence protocol as part of the I/O protocol.

3. The system of claim 1, wherein the logic circuitry of an HMC device is configured to communicate packetized information as part of an I/O protocol used to access the memory die and include memory coherence state information with the packetized information.

4. The system of claim 3, wherein the logic circuitry of an HMC device is configured to communicate address information as part of the packetized information and to include memory coherence state information with the address information.

5. The system of claim 1, wherein the logic circuitry of an HMC device is configured to determine modified state information, shared state information, and invalid state information for a word of memory of the memory die and store the state information in association with the word of memory of the memory die.

6. The system of claim 1, wherein the logic circuitry of an HMC device is configured to determine at least one of exclusivity state information and ownership state information for a word of memory of the memory die and store the state information in association with the word of shared memory data.

7. The system of claim 1, including at least one HMC device configured as a hub HMC device, wherein logic circuitry of the hub HMC device adds routing information to a packetized message and the logic circuitry of a receiving HMC device uses the source information to determine memory coherence state information.

8. The system of claim 1, wherein the logic circuitry of the HMC device is configured to, upon receiving a request for exclusive access to a memory word, initiate a request packet from the HMC device to a processor with ownership of the memory word.

9. The system of claim 1, wherein the memory controller of the logic base die of an HMC is configured to manage 3D access to memory of the memory die by at least one processor and by another HMC device.

10. The system of claim 1, wherein the memory die of an HMC device include memory arranged as a plurality of vaults and the logic base die includes a memory controller for each vault of the memory die.

11. The system of claim 1, wherein the processors of the plurality of host processors are system-on-chip (SoC) processors.

12. A hybrid memory cube (HMC) device including:

a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the of the memory die is mapped to include at least a portion of a memory coherence directory; and

a logic base die including at least one memory controller configured to manage three-dimensional (3D) access by at least one second device to memory of the plurality of memory die, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.

13. The HMC device of claim 12, wherein the logic circuitry of the logic base die is configured to implement the memory coherence protocol as part of an input/output (I/O) protocol used to access the memory die.

14. The HMC device of claim 12, wherein the logic circuitry of the logic base die is configured to communicate address information as part of the I/O protocol and include memory coherence state information with the address information.

15. The HMC device of claim 12, wherein the logic circuitry of the logic base die is configured to determine modified state information, shared state information, and invalid state information for a word of memory of the memory die and store the state information in association with the word of memory of the memory die.

16. The HMC device of claim 12, wherein the logic circuitry of the logic base die is configured to determine at least one of exclusivity state information and ownership state information for a word of memory of the memory die and store the state information is association with the word of shared memory data.

17. The HMC device of claim 12, wherein the memory controller of the logic base die is configured to manage 3D access by at least one processor and by another HMC device.

18. The HMC device of claim 12, wherein the memory die include memory arranged as a plurality of vaults and the logic base die includes a memory controller for each vault of the memory die.

19. A method of operating a computer system, the method comprising:

managing access to a distributed shared memory of the computer system, wherein the shared memory is configured for three dimensional access;

storing memory coherence state information in the distributed shared memory as a memory coherence directory;

communicating packetized information between a plurality of processors and shared memory of the computing system; and

including memory coherence state information with the communicated packetized information.

20. The method of claim 19, wherein including memory coherence state information with the communicated packetized information includes incorporating the memory coherence state information into an address field of the packetized information.

21. The method of claim 19, including implementing a memory coherence protocol using the communicated packetized information, wherein memory coherence state information of the memory coherence directory is modified by the shared memory using the memory coherence protocol.

22. The method of claim 19, wherein storing memory coherence state information in the shared memory includes storing the memory coherence state information with a shared memory data word.

23. The method of claim 19, wherein storing memory coherence state information in the shared memory includes storing a modified bit, a shared bit, and an invalid bit with the shared memory data word.

24. The method of claim 19, wherein storing memory coherence state information in the shared memory includes storing at least one of exclusivity information and ownership information with the shared memory data word.

25. The method of claim 19, including modifying the memory coherence state information using a logic base layer that includes at least one memory controller for the shared memory.

26. The method of claim 19, including modifying the memory coherence state information using an atomic memory operation.

27. The method of claim 19, including requesting, by a processor of the plurality of processors, a specific state of a memory word of target HMC device;

and initiating a response from the target HMC device to one or more processors of the plurality of processors.