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HYBRID MEMORY CUBE SYSTEM INTERCONNECT DIRECTORY-BASED CACHE COHERENCE METHODOLOGY

  • US 20150324290A1
  • Filed: 05/07/2015
  • Published: 11/12/2015
  • Est. Priority Date: 05/08/2014
  • Status: Active Grant
First Claim
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1. A computing system comprising:

  • a plurality of host processors; and

    a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors, an HMC device including;

    a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and

    a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.

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