NEURAL NETWORK CONNECTIONS USING NONVOLATILE MEMORY DEVICES

• US 20150324691A1
• Filed: 05/05/2015
• Published: 11/12/2015
• Est. Priority Date: 05/07/2014
• Status: Abandoned Application

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Dropps, Frank, Khoueir, Antoine, Gomez, Kevin Arthur, Trantham, Jon
• Application Number:
  US14/704,124
• Publication Number:
  US 20150324691A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/08 Learning methods

Abstract

A system includes a plurality of nonvolatile memory cells and a map that assigns connections between nodes of a neural network to the memory cells. Memory devices containing nonvolatile memory cells and applicable circuitry for reading and writing may operate with the map. Information stored in the memory cells can represent weights of the connections. One or more neural processors can be present and configured to implement the neural network.

Claims

1. A system, comprising:

a plurality of nonvolatile memory cells; and

a map that assigns connections between nodes of a neural network to the memory cells.

2. The system of claim 1, wherein the memory cells are selected from the group consisting of floating gate memory cells and charge trap memory cells, and are arranged in a memory cell array of a flash memory device.

3. The system of claim 1, further comprising read/write circuitry configured to read information from and store information to the memory cells.

4. The system of claim 3, wherein during a read operation, the read/write circuitry is configured to:

sense a voltage indicating an amount of charge stored on each memory cell, the amount of charge representing a weight of the connection; and

compare the voltage to a threshold to determine the amount of charge.

5. The system of claim 3, wherein during a write operation, the read/write circuitry is configured to apply voltage pulses that store an amount of charge on each memory cell, the amount of charge representing a weight of the connection.

6. The system of claim 1, wherein each memory cell stores charge corresponding to 2ⁿ voltage levels.

7. The system of claim 6, wherein n is greater than 2.

8. The system of claim 1, further comprising one or more neural processors configured to implement the neural network.

9. The system of claim 8, wherein the neural processors are configured to assign a weight to each connection of the neural network.

10. The system of claim 8, wherein the neural processors are configured to dynamically update the connectivity of the neural network and to dynamically update the map to reflect the updated connectivity.

11. The system of claim 1, wherein the map is static.

12. A system, comprising:

a memory device comprising;

a plurality of nonvolatile memory cells;

circuitry configured to read information from and write information to the memory cells;

a map that assigns connections between nodes of a neural network to memory cells of the memory device, the information stored in the memory cells representing weights of the connections;

a controller configured to control read and write operations of the memory cells; and

one or more neural processors configured to implement the neural network.

13. The system of claim 12, wherein the neural processors are configured to dynamically update the connections of the map.

14. The system of claim 12, wherein:

the neural network dynamically updates the weights of the connections; and

the controller causes the updated weights to be stored in the memory cells based on the map.

15. The system of claim 12, wherein the controller causes the information to be read from the memory cells as requested by the neural processors.

16. The system of claim 12, wherein the memory device is one of NAND flash, NOR flash, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM) or spin-torque random access memory (STRAM).

17. A method, comprising:

mapping connections between nodes of a neural network to nonvolatile memory cells of a memory device;

storing information in the memory cells that represents the connection weights;

reading the information from the memory cells; and

operating the neural network using the information.

18. The method of claim 17, wherein the mapping step is a one-to-one mapping.

19. The method of claim 17, further comprising dynamically updating the connection weights.

20. The method of claim 17, wherein operating the neural network comprises:

reading the information stored in the memory cells; and

using the information to implement the neural network.