IN-MEMORY LIGHTWEIGHT COHERENCY

• US 20150325272A1
• Filed: 05/07/2015
• Published: 11/12/2015
• Est. Priority Date: 05/08/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Murphy, Richard C.
• Granted Patent: US 10,825,496 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

Claims

1. A computing system comprising:

a plurality of host processors;

a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die mapped to include at least a portion of a memory coherence directory; and

a logic base die packaged with at least the first memory die and the second memory die, the logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

2. The computing system of claim 1, including a plurality of hybrid memory cube (HMC) devices, wherein an HMC device includes at least the first memory die, the second memory die, and the logic base die.

3. The computing system of claim 2, wherein the logic circuitry of an HMC device is configured to communicate packetized information using an input/output (I/O) protocol used to access the memory die and implement a memory coherence protocol as part of the I/O protocol.

4. The system of claim 3, wherein the logic circuitry of an HMC device is configured to route packetized information as part of the I/O protocol and detect memory coherence state information included with the packetized information.

5. The system of claim 2, wherein the logic circuitry of an HMC device is configured to determine modified state information, shared state information, and invalid state information for a word of memory of the memory die and store the state information in association with the word of memory of the memory die.

6. The system of claim 2, wherein the logic circuitry of an HMC device is configured to determine at least one of exclusivity state information and ownership state information for a word of memory of the memory die and store the state information in association with the word of shared memory data.

7. The system of claim 2, including at least one HMC device configured as a hub HMC device, wherein logic circuitry of the hub HMC device adds routing information to a packetized message and detects memory coherence state information in the packetized message.

8. The system of claim 2, wherein the memory controller of the logic base die of an HMC is configured to manage 3D access to memory of the memory die by at least one processor and by another HMC device.

9. The system of claim 2, wherein the memory die of an HMC device include memory arranged as a plurality of vaults and the logic base die includes a memory controller for each vault of the memory die.

10. The system of claim 1, wherein the processors of the plurality of host processors are system-on-chip (SoC) processors.

11. A method of operating a computer system, the method comprising:

managing access to a distributed shared memory of the computer system, wherein the shared memory is configured for three dimensional access;

determining, by the distributed shared memory, memory coherence state information resulting from memory access;

communicating packetized information among a plurality of processors and shared memory endpoints of the computing system and including the memory coherence state information with the communicated packetized information; and

tracking the memory coherence state information using the shared memory endpoints.

12. The method of claim 11, wherein tracking the memory coherence state information using the shared memory endpoints includes tracking the memory coherence state information using hybrid memory cube (HMC) devices that include the shared memory.

13. The method of claim 11, including storing the memory coherence state information with a shared memory data word.

14. The method of claim 11, including modifying the memory coherence state information using a logic base layer that includes at least one memory controller for the shared memory.

15. The method of claim 11, wherein storing memory coherence state information in the shared memory includes storing a modified bit, a shared bit, and an invalid bit with the shared memory data word.

16. An electronic device of a single electronic device package, the electronic device including:

a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the of the memory die is mapped to include at least a portion of a memory coherence directory; and

a logic base die packaged with the plurality of integrated circuit memory die, the logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

17. The electronic device of claim 16, wherein the electronic device is a hybrid memory cube (HMC) device.

18. The electronic device of claim 17, wherein the logic circuitry of the logic base die is configured to communicate packetized information using an input/output (I/O) protocol used to access the memory die and implement a memory coherence protocol as part of the I/O protocol.

19. The electronic device of claim 18, wherein the logic circuitry of the logic base die is configured to route packetized information as part of the I/O protocol and detect memory coherence state information included with the packetized information.

20. The electronic device of claim 17, wherein the logic circuitry of the logic base die is configured to determine modified state information, shared state information, and invalid state information for a word of memory of the memory die and store the state information in association with the word of memory of the memory die.

21. The electronic device of claim 17, wherein the logic circuitry of the logic base die is configured to determine at least one of exclusivity state information and ownership state information for a word of memory of the memory die and store the state information in association with the word of shared memory data.