System And Method To Reducing Disturbances During Programming Of Flash Memory Cells

• US 20150325300A1
• Filed: 05/12/2014
• Published: 11/12/2015
• Est. Priority Date: 05/12/2014
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Kim, Jinho, Ly, Anh, Markov, Victor
• Granted Patent: US 9,418,744 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An improved control gate decoding design for reducing disturbances during the programming of flash memory cells is disclosed. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.

Claims

1. A flash memory system, comprising:

a first sector comprising a first plurality of rows of flash memory cells, the first sector associated with a first source line;

a second sector comprising a second plurality of rows of flash memory cells, the second sector associated with a second source line; and

a control gate line decoder coupled to a control gate voltage source and selectively coupled to a control gate line associated with one of the first plurality of rows and a control gate line associated with one of the second plurality of rows.

2. The flash memory system of claim 1, wherein the first sector is associated with a first erase gate line and the second sector is associated with a second erase gate line.

3. The flash memory system of claim 1, wherein each of the first plurality of rows is associated with a different control gate line.

4. The flash memory system of claim 3, wherein each of the second plurality of rows is associated with a different control gate line.

5. The flash memory system of claim 1, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

6. The flash memory system of claim 2, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

7. The flash memory system of claim 3, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

8. The flash memory system of claim 4, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

9. A method of programming a flash memory cell, comprising:

activating a selected flash memory cell in a first sector using a first word line and a first bit line;

coupling a control gate voltage source to a control gate of the selected flash memory cell using a control gate line decoder, wherein the control gate line decoder can be selectively coupled to a control gate of one or more flash memory cells outside of the first sector; and

storing a digital value in a floating gate of the selected flash memory cell.

10. The method of claim 9, further comprising erasing the selected flash memory cell using an erase gate line.

11. The flash memory system of claim 9, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

12. The flash memory system of claim 10, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

13. A method of programming and reading a flash memory cell, comprising:

activating a selected flash memory cell in a first sector using a first word line and a first bit line;

coupling a control gate voltage source to a control gate of the selected flash memory cell using a control gate line decoder, wherein the control gate line decoder can be selectively coupled to a control gate of one or more flash memory cells outside of the first sector;

storing a digital value in a floating gate of the selected flash memory cell; and

reading the digital value using a source line of the selected flash memory cell.

14. The method of claim 13, wherein the storing step comprises adding electrons to the floating gate.

15. The method of claim 13, further comprising erasing the selected flash memory cell using an erase gate line.

16. The method of claim 15, wherein the erasing step comprises removing electrons from the floating gate.

17. The flash memory system of claim 13, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

18. The flash memory system of claim 14, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

19. The flash memory system of claim 15, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.

20. The flash memory system of claim 16, wherein the first plurality of rows of flash memory cells and the second plurality of rows of flash memory cells each comprise split gate flash memory cells.