SEMICONDUCTOR FABRICATION METHOD

• US 20150325441A1
• Filed: 10/09/2014
• Published: 11/12/2015
• Est. Priority Date: 05/09/2014
• Status: Abandoned Application

• Current Assignee: Powerchip Technology Corporation
• Original Assignee: Powerchip Technology Corporation
• Inventors: Tai, Hsin, Liao, Yu-Mei, Liu, Wei-Ting, Peng, Wen-Chuan
• Application Number:
  US14/510,120
• Publication Number:
  US 20150325441A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks

Abstract

A semiconductor fabrication method is provided. A substrate having thereon a base layer, a hard mask layer, and a core layer is prepared. A resist pattern is transferred to the core layer, thereby forming a core pattern. The core pattern is subjected to a post-clean process. Thereafter, a spacer layer is deposited on the core pattern. The spacer layer is etched to form spacer pattern on each sidewall of the core pattern. The core pattern is then removed. The spacer pattern is transferred to the underlying hard mask layer and the base layer.

Claims

1. A semiconductor fabrication method, comprising:

providing a substrate having thereon a base layer, a hard mask layer on the base layer, and a core layer on the hard mask layer;

forming a resist pattern on the core layer;

performing a first anisotropic dry etching process to transfer the resist pattern into the core layer, thereby forming a core pattern;

after forming the core pattern, performing a pattern trimming process to trim the core pattern;

subjecting the core pattern to a post-clean process to remove polymeric residuals generated during the first anisotropic dry etching process;

after the post-clean process, depositing a spacer layer on the core pattern;

performing a second anisotropic dry etching process to etch the spacer layer, thereby forming a spacer pattern on each sidewall of the core pattern;

removing the core pattern; and

performing a third anisotropic dry etching process to transfer the spacer pattern into the hard mask layer.

2. The semiconductor fabrication method according to claim 1 wherein the base layer comprises a silicon substrate, a polysilicon layer, a metal layer or a dielectric layer.

3. The semiconductor fabrication method according to claim 1 wherein the hard mask layer comprises polysilicon or silicon nitride.

4. The semiconductor fabrication method according to claim 1 wherein the core layer comprises an amorphous carbon layer.

5. The semiconductor fabrication method according to claim 1 wherein the post clean process includes making the core pattern contact with a pre-determined cleaning solution at a pre-determined temperature for a pre-determined time period.

6. The semiconductor fabrication method according to claim 5 wherein the pre-determined cleaning solution comprises SPM solution, APM solution, dilute APM solution, dilute hydrofluoric acid, isopropyl alcohol, dilute sulfuric acid and hydrogen peroxide mixture (DSP), or a dilute mixture of sulfuric acid, hydrogen peroxide and hydrofluoric acid (DSP+).

7. The semiconductor fabrication method according to claim 5 wherein the pre-determined temperature ranges between room temperature and 165°

C.

8. The semiconductor fabrication method according to claim 5 wherein the pre-determined time period ranges between 20 seconds and 3 minutes.

10. The semiconductor fabrication method according to claim 1 wherein the spacer layer is deposited at a deposition temperature that is equal to or greater than 400°

C.

9. (canceled)