METHOD FOR INTERCONNECTING STACKED SEMICONDUCTOR DEVICES

• US 20150325550A1
• Filed: 09/27/2013
• Published: 11/12/2015
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation, Junfeng Zhao
• Inventors: Zhao, Jungeng
• Granted Patent: US 9,627,358 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

Claims

1. A method for making a stacked semiconductor device comprising:

forming rims on a first die and a second die, the rims extending laterally away from the first and second dice;

stacking the second die over the first die; and

drilling one or more vias through the rims after stacking, the one or more vias extending between the first and second dice.

2. The method of claim 1 further comprising filling the one or more vias with a conductive material to electrically interconnect the first and second dice.

3. The method of claim 1, wherein forming rims includes forming a dielectric portion over the first die and the second die, the rims formed with the dielectric portion.

4. The method of claim 3, wherein forming the dielectric portion includes molding resin around the first die and the second die, the rims formed with the resin.

5. The method of claim 1 comprising:

forming a first reconstituted dice panel including a first plurality of dice molded in a panel frame, the first plurality of dice including the first die, and

forming a second reconstituted dice panel including a second plurality of dice molded in another panel frame, the second plurality of dice including the second die; and

forming rims includes surrounding a periphery of the dice in the first and second reconstituted dice panels with a dielectric material.

6. The method of claim 5 comprising sorting the dice in the first plurality of dice and second plurality of dice to ensure only operational dice are used to form the first and second reconstituted dice panels.

7. The method of claim 6 comprising separating individual stacks of first and second adhered dice from the first and second reconstituted dice panels.

8. The method of claim 1, wherein drilling the one or more vias consists of one or more of laser drilling, mechanical drilling or chemical etching.

9. The method of claim 1, wherein drilling the one or more vias is continuous through the first and second dice.

10. The method of claim 1 comprising forming one or more redistribution layers of conductive traces over one or more of the first or second dice or the rims, the one or more vias in communication with the conductive traces at the rims.

11. The method of claim 1, wherein stacking the first die over the second die includes staggering the second die relative to the first die to expose at least one bond pad of the second die.

12. The method of claim 11, wherein drilling the one or more vias includes drilling at least one via through the rim of the first die, the at least one via extending to the at least one bond pad of the second die.

13. A method for making a stacked semiconductor device comprising:

sorting dice into a plurality of operational dice, the plurality of operational dice tested for operability; and

forming at least a first reconstituted dice panel including;

arranging the sorted plurality of operational dice within a panel frame, and

molding a resin around the plurality of operational dice within the panel frame to form the first reconstituted dice panel, rims formed with the resin extend laterally from each of the plurality operational dice.

14. The method of claim 13 comprising repeating arranging and molding to form a second reconstituted dice panel, rims extend laterally away from each die of the plurality of operational dice of the second reconstituted dice panel.

15. The method of claim 14 comprising coupling the first reconstituted dice panel to the second reconstituted dice panel;

and

drilling one or more vias in the coupled first and second reconstituted dice panels, the one or more vias within the rims of the plurality of operational dice and the one or more vias extend between the first and second reconstituted dice panels.

16. The method of claim 15, wherein coupling the first reconstituted dice panel to the second reconstituted dice panel includes aligning the pluralities of operational dice of each of the first and second reconstituted dice panels.

17. The method of claim 15 comprising separating the first and second reconstituted dice panels into a plurality of multi-layered packages, each of the multi-layered packages including:

at least two dice of the plurality of operational dice of the first and second reconstituted dice panels, and

at least one via of the one or more vias.

18. The method of claim 15, wherein drilling one or more vias in the coupled first and second reconstituted dice panels includes drilling one or more vias through the rims of the plurality of operational dice.

19. The method of claim 15 comprising filling the one or more vias with a conductive material to electrically couple the first and second reconstituted dice panels.

20. The method of claim 13, wherein forming at least the first reconstituted dice panel includes forming one or more redistribution layers of conductive traces over the plurality of operational dice and the respective rims, the one or more vias in communication with the conductive traces at the rims.

21. The method of claim 13, wherein arranging the sorted plurality of operational dice within the panel frame includes arranging the sorted plurality of operational dice into one or more staggered stacks of dice within the panel frame, each of the one or more staggered stacks of dice including two or more dice and at least one of the two or more dice is staggered relative to an adjacent die.

22. The method of claim 21, wherein molding the resin around the plurality of operation dice includes molding the resin around each of the one or more staggered stacks of dice.

23. A stacked semiconductor device comprising:

a first die;

a second die stacked over the first die;

rims extending laterally away from each of the first and second dice;

a first redistribution layer extending over the first die and the rim of the first die; and

one or more vias extending through at least one of the respective rims, the one or more vias in communication with the first and second dice through the rims.

24. The stacked semiconductor device of claim 23, wherein the respective rims are molded resin rims molded around the respective first and second dice, the one or more vias extend through at least one of the molded resin rims.

25. The stacked semiconductor device of claim 23 comprising dielectric portions formed over each of the first and second dice, the dielectric portions including the one or more rims, and the one or more vias extend through the dielectric portions.

26. The stacked semiconductor device of claim 23, wherein the one or more vias are laterally spaced from the first and second dice.

27. The semiconductor device of claim 23 comprising a second redistribution layer extending over the second die and the rim of the second die.

28. The stacked semiconductor device of claim 27, the first and second redistribution layers provide a fan-out configuration of conductive traces extending over and beyond respective footprints of the first and second dice, and the one or more vias are in communication with the first and second redistribution layers.

29. The stacked semiconductor device of claim 23, wherein the vias are drilled vias formed in at least one of the respective rims after stacking of the second die over the first die.

30. The stacked semiconductor device of claim 23 comprising a plurality of dice including the first and second dice, rims extend laterally from each of the plurality of dice, the plurality of dice are in a stacked configuration, and the one or more vias extend through at least two of the respective rims of the plurality of dice.

31. The stacked semiconductor device of claim 23, wherein the second die is staggered relative to the first die, the second die include at least one exposed bond pad according to the staggering.

32. The stacked semiconductor device of claim 31, wherein the one or more vias extend through the rim of the first die to the at least one exposed bond pad of the second die.