SEMICONDUCTOR DEVICES INCLUDING A DUMMY GATE STRUCTURE ON A FIN

• US 20150325575A1
• Filed: 03/05/2015
• Published: 11/12/2015
• Est. Priority Date: 05/08/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Do-Hyoung Kim, Kee-Sang Kwon, Kyoung-Hwan Yeo
• Inventors: Park, Sang-Jine, Kwon, Kee-Sang, Kim, Do-Hyoung, Yoon, Bo-Un, Bai, Keun-Hee, Yeo, Kyoung-Hwan, Jeon, Yong-Ho, Yang, Kwang-Yong
• Granted Patent: US 9,299,700 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

Claims

1. A semiconductor device comprising:

a fin protruding from a substrate and extending in a direction;

a recess in the fin;

a device isolation layer filling the recess;

a dummy gate structure overlapping the device isolation layer;

first and second spacers at opposite sides of the dummy gate structure on the fin;

an inner spacer on inner sidewalls of the first and second spacers; and

a source/drain region at opposite sides of the recess and spaced apart from the device isolation layer.

2. The semiconductor device of claim 1, wherein a first width of the recess is narrower than a second width of the dummy gate structure.

3. The semiconductor device of claim 2, wherein a first bottom surface of the recess is lower than a second bottom surface of the source/drain region.

4. The semiconductor device of claim 1, wherein:

the first spacer comprises a first region and a second region on the first region;

the second spacer comprises a third region and a fourth region on the third region;

a first width of the first region is wider than a second width of the second region; and

a third width of the third region is wider than a fourth width of the fourth region.

5. The semiconductor device of claim 4, wherein a first distance between the first region and the third region is shorter than a second distance between the second region and the fourth region.

8. The semiconductor device of claim 1, further comprising a capping layer between the recess and the device isolation layer and continuously extending adjacent a boundary of the recess.

9. The semiconductor device of claim 1, further comprising a cover layer on a top surface of the dummy gate structure.

10. The semiconductor device of claim 9, wherein the first and second spacers extend along respective sidewalls of the cover layer.

11. The semiconductor device of claim 1, wherein a top surface of the device isolation layer protrudes beyond or is coplanar with a top surface of the fin.

12. The semiconductor device of claim 11,

wherein the device isolation layer comprises a first region in the recess and a second region on the first region, and

wherein a first width of the first region is narrower than a second width of the second region.

13. The semiconductor device of claim 1, further comprising a first gate structure and a second gate structure spaced apart from the dummy gate structure at opposite sides, respectively, of the dummy gate structure on the fin.

14. The semiconductor device of claim 13, wherein a bottom surface of the dummy gate structure is higher than or coplanar with respective bottom surfaces of the first and second gate structures.

6. (canceled)

7. (canceled)

15. A semiconductor device comprising:

a fin protruding from a substrate and extending in a direction;

a recess in the fin;

a dummy gate structure filling the recess;

first and second gate structures at opposite sides of the dummy gate structure, respectively, wherein the first and second gate structures are spaced apart from the dummy gate structure on the fin and extend over the fin;

a first spacer on the first gate structure, a second spacer on the second gate structure, and a third spacer comprising respective portions on the opposite sides of the dummy gate structure; and

an inner spacer between the dummy gate structure and the third spacer.

16. The semiconductor device of claim 15, wherein a first width of the recess is narrower than a second width of the dummy gate structure on the recess.

17. The semiconductor device of claim 15,

wherein the dummy gate structure comprises a gate insulation layer, a barrier layer and a gate electrode, and

wherein the gate electrode is in the recess.

18-20. -20. (canceled)

21. A semiconductor device comprising:

a fin protruding from a substrate;

a source/drain region in the fin;

a device isolation layer in a recess region of the fin that is between and spaced apart from first and second portions of the source/drain region;

a dummy gate structure overlapping the device isolation layer; and

a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

22. The semiconductor device of claim 21, further comprising first and second gate structures on the fin, wherein the dummy gate structure is between the first and second gate structures.

23. The semiconductor device of claim 22, further comprising a protective cover layer on the dummy gate structure and the first and second gate structures.

24. The semiconductor device of claim 21,

wherein the spacer comprises a first spacer, and

wherein the semiconductor device further comprises a second spacer that is on a sidewall of the first spacer and that undercuts a portion of the dummy gate structure.

25. The semiconductor device of claim 21, wherein the device isolation layer is tapered away from the dummy gate structure.