CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION

• US 20150327367A1
• Filed: 05/12/2014
• Published: 11/12/2015
• Est. Priority Date: 05/12/2014
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: SHEN, Hong, Sun, Zhuowen, Woychik, Charles G., Sitaram, Arkalgud
• Granted Patent: US 9,402,312 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/498 : Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/538 : the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 : Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/1615 : Shape
• CPC Class Codes: H01L 2924/16153 : Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/0271 : Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/181 : associated with surface mounted components

Abstract

A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Claims

1. A circuit assembly comprising:

a combined interposer comprising a plurality of constituent interposers, each constituent interposer comprising a substrate, the substrates being laterally spaced from each other;

wherein the combined interposer comprises a first circuit layer comprising circuitry and physically contacting a top surface of two or more of the substrates, the circuitry comprising a circuit extending over at least two of said two or more of the substrates;

wherein for each of two or more of the constituent interposers, the constituent interposer comprises a first constituent circuit layer which is part of the first circuit layer, the first constituent circuit layer being present on a top surface of the constituent interposer'"'"'s substrate, the first constituent circuit layer comprising circuitry;

wherein the first circuit layer comprises first contact pads on top;

wherein the circuit assembly further comprises one or more circuit modules at least one of which comprises an integrated circuit, the one or more circuit modules overlying the first circuit layers, each circuit module comprising one or more contact pads attached to one or more first contact pads.

2. The circuit assembly of claim 1 wherein at least a portion of at least one first contact pad overlies a gap separating at least two of the adjacent substrates from each other.

3. The circuit assembly of claim 1 wherein the first circuit layer comprises a circuit connected to first contact pads located over different ones of the substrates.

4. The circuit assembly of claim 1 wherein the combined interposer comprises a second circuit layer comprising circuitry and physically contacting a bottom surface of one or more of the substrates;

wherein for each of one or more of the constituent interposers, the constituent interposer comprises a second constituent circuit layer which is part of the second circuit layer, the second constituent circuit layer being present on a bottom surface of the constituent interposer'"'"'s substrate, the second constituent circuit layer comprising circuitry;

wherein the second circuit layer comprises each second constituent circuit layer;

wherein the second circuit layer comprises second contact pads on the bottom;

wherein one or more of the constituent interposers each comprise one or more conductive through-paths passing through the constituent interposers'"'"' substrates, each conductive through-path being connected to at least one first constituent circuit layer and at least one second constituent circuit layer.

5. The circuit assembly of claim 4 wherein at least a portion of at least one second contact pad underlies a gap separating at least two of the adjacent substrates from each other.

6. The circuit assembly of claim 4 wherein the second circuit layer comprises a circuit extending under different substrates.

7. The circuit assembly of claim 6 wherein at least one of the first and second circuit layers comprises a circuit connected to conductive through-paths of different constituent interposers.

8. The circuit assembly of claim 1 wherein a gap separating the substrates from each other has a higher CTE and/or lower elasticity modulus and/or lower stiffness than each of the substrates.

9. A method for manufacturing a circuit assembly, the method comprising:

forming a groove pattern comprising one or more grooves in a top surface of a substrate, the groove pattern separating a plurality of substrate regions from each other, the substrate regions being joined together by the substrate'"'"'s bottom portion underlying the groove pattern;

forming a first circuit layer overlying the substrate regions and the groove pattern, the first circuit layer comprising circuitry with first contact pads on top, the circuitry overlapping the groove pattern;

attaching one or more circuit modules to the first contact pads; and

removing at least part of the substrate'"'"'s bottom portion underlying the groove pattern so that the substrate regions are no longer joined together by the substrate.

10. The method of claim 9 further comprising, before removing at least part of the substrate'"'"'s bottom portion, forming in the groove pattern a material having a higher CTE and/or lower elasticity modulus and/or lower stiffness than each of the substrate regions.

11. The method of claim 10 wherein the material has a planar surface which, together with top surfaces of the substrate regions, provides a common planar surface underlying and physically contacting the first circuit layer.

12. The method of claim 9 further comprising:

after removing at least part of the substrate'"'"'s bottom portion, forming a second circuit layer underlying the substrate regions and the groove pattern, the second circuit layer comprising circuitry with second contact pads on the bottom, the circuitry overlapping the groove pattern;

forming one or more conductive through-paths passing through one or more of the substrate regions, each conductive through-path being connected to the first and second circuit layers.

13. A method for manufacturing a circuit assembly, the method comprising:

forming a first circuit layer overlying a substrate, the first circuit layer comprising circuitry with first contact pads on top;

attaching one or more circuit modules to the first contact pads; and

then

removing material from the substrate'"'"'s bottom to obtain from the substrate a plurality of substrate regions spaced from each other and not joined together by the substrate, and to form a gap pattern comprising one or more gaps separating the substrate regions from each other, the first circuit layer not being removed, the circuitry overlapping at least one of the substrate regions and the gap pattern.

14. The method of claim 13 further comprising, after removing material from the substrate'"'"'s bottom, forming in the gap pattern a material having a higher CTE and/or lower elasticity modulus and/or lower stiffness than each of the substrate regions.

15. The method of claim 13 further comprising:

forming a second circuit layer underlying the substrate regions and the gap pattern, the second circuit layer comprising circuitry with second contact pads on the bottom, the circuitry overlapping the gap pattern;

forming one or more conductive through-paths passing through one or more of the substrate regions, each conductive through-path being connected to the first and second circuit layers.

16. A circuit assembly comprising:

a combined interposer comprising a plurality of constituent interposers, each constituent interposer comprising a substrate, the substrates being laterally spaced from each other;

wherein the combined interposer comprises a first circuit layer comprising circuitry and physically contacting a top surface of one or more of the substrates;

wherein for each of one or more of the constituent interposers, the constituent interposer comprises a first constituent circuit layer which is part of the first circuit layer, the first constituent circuit layer being present on a top surface of the constituent interposer'"'"'s substrate, the first constituent circuit layer comprising circuitry;

wherein the first circuit layer comprises each first constituent circuit layer, and continuously extends from at least one first constituent circuit layer laterally beyond the corresponding substrate;

wherein the first circuit layer comprises first contact pads on top;

wherein the circuit assembly further comprises one or more circuit modules at least one of which comprises an integrated circuit, the one or more circuit modules overlying the first circuit layers, each circuit module comprising one or more contact pads attached to one or more first contact pads.

17. The circuit assembly of claim 16 wherein the first circuit layer comprises a circuit connected to first contact pads which are not located over any single one of the substrates.

18. The circuit assembly of claim 16 wherein the combined interposer comprises a second circuit layer comprising circuitry and physically contacting a bottom surface of one or more of the substrates;

wherein for each of one or more of the constituent interposers, the constituent interposer comprises a second constituent circuit layer which is part of the second circuit layer, the second constituent circuit layer being present on a bottom surface of the constituent interposer'"'"'s substrate, the second constituent circuit layer comprising circuitry;

wherein the second circuit layer comprises each second constituent circuit layer;

wherein the second circuit layer comprises second contact pads on the bottom;

wherein one or more of the constituent interposers each comprise one or more conductive through-paths passing through the constituent interposers'"'"' substrates, each conductive through-path being connected to at least one first constituent circuit layer and at least one second constituent circuit layer.

19. The circuit assembly of claim 18 further comprising a circuit element passing between at least two of the substrates, for connecting a contact pad or other circuit element above the substrates to a contact pad or other circuit element below the substrates.