HVAC CONTROLLER HAVING MULTIPLEXED INPUT SIGNAL DETECTION AND METHOD OF OPERATION THEREOF

• US 20150331432A1
• Filed: 04/21/2015
• Published: 11/19/2015
• Est. Priority Date: 05/19/2014
• Status: Active Grant

• Current Assignee: Lennox Industries Incorporated (Lennox International Incorporated), NVIDIA Corporation
• Original Assignee: Lennox Industries Incorporated (Lennox International Incorporated)
• Inventors: Hadzidedic, Darko, Murugesan, Sakthi Narayan Kumar
• Granted Patent: US 10,338,545 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05B 15/02 electric
• CPC Class Codes: G05B 2219/2642 Domotique, domestic, home control, automation, smart house
• CPC Class Codes: G05D 23/19 characterised by the use of electric means G05D23/1393 takes precedence

Abstract

A heating, ventilation and air conditioning (HVAC) controller, a method of detecting multiplexed input signals and an HVAC system employing the controller or the method. In one embodiment, the HVAC controller includes: (1) a signal conditioner configured to convert received alternating current (AC) input signals into corresponding square wave signals of a digital logic voltage, (2) a multiplexer coupled to the signal conditioner and configured to select one of the square wave signals and (3) a sample analyzer coupled to the multiplexer and configured to evaluate multiple samples of the selected one of the square wave signals to derive a binary state.

Claims

1. An HVAC controller, comprising:

a signal conditioner configured to convert received alternating current (AC) input signals into corresponding square wave signals of a digital logic voltage;

a multiplexer coupled to said signal conditioner and configured to select one of said square wave signals; and

a sample analyzer coupled to said multiplexer and configured to evaluate multiple samples of said selected one of said square wave signals to derive a binary state.

2. The controller as recited in claim 1 wherein said multiplexer is further coupled to an interrupt pin of a processor and said sample analyzer is embodied in a selected one of interrupt-handling software and firmware executing in said processor.

3. The controller as recited in claim 1 wherein said sample analyzer is further configured to provide said binary state to an interrupt pin of a processor.

4. The controller as recited in claim 3 wherein said sample analyzer comprises a gate and a counter and is configured to employ a clock signal to sample said selected one of said square wave signals and assert a signal on said interrupt pin if at least a threshold number of assertions is reached during a window of time.

5. The controller as recited in claim 4 wherein said threshold number of assertions is 20.

6. The controller as recited in claim 1 wherein said AC input signals are at a control voltage and said square wave signals are at a digital logic voltage.

7. The controller as recited in claim 1 wherein said multiplexer is configured to select among said square wave signals in a round-robin manner.

8. A method of detecting multiplexed input signals, comprising:

converting received AC input signals into corresponding square wave signals of a digital logic voltage;

selecting one of said square wave signals; and

evaluating multiple samples of said selected one of said square wave signals to derive a binary state.

9. The method as recited in claim 8 wherein said selecting comprises providing said one of said square wave signals to an interrupt pin of a processor and said evaluating is carried out by a selected one of interrupt-handling software and firmware executing in said processor.

10. The method as recited in claim 8 wherein said evaluating comprises providing said binary state to an interrupt pin of a processor.

11. The method as recited in claim 10 wherein said evaluating comprises:

employing a clock signal to sample said selected one of said square wave signals; and

asserting a signal on said interrupt pin if at least a threshold number of assertions is reached during a window of time.

12. The method as recited in claim 11 wherein said threshold number of assertions is 20.

13. The method as recited in claim 8 wherein said AC input signals are at a control voltage and said square wave signals are at a digital logic voltage.

14. The method as recited in claim 8 wherein said selecting is carried out in a round-robin manner.

15. An HVAC system, comprising:

a compressor;

a furnace associated with said compressor;

a blower associated with said compressor and furnace; and

a controller associated with said compressor, said furnace and said blower, said controller having;

a signal conditioner configured to convert AC input signals from at least one of said compressor, said furnace and said blower into corresponding square wave signals of a digital logic voltage,

a multiplexer coupled to said signal conditioner and configured to select one of said square wave signals, and

a sample analyzer coupled to said multiplexer and configured to evaluate multiple samples of said selected one of said square wave signals to derive a binary state for controlling at least one of said compressor, said furnace and said blower.

16. The system as recited in claim 15 wherein said multiplexer is further coupled to an interrupt pin of a processor and said sample analyzer is embodied in a selected one of interrupt-handling software and firmware executing in said processor.

17. The system as recited in claim 15 wherein said sample analyzer is further configured to provide said binary state to an interrupt pin of a processor.

18. The system as recited in claim 17 wherein said sample analyzer comprises a gate and a counter and is configured to employ a clock signal to sample said selected one of said square wave signals and assert a signal on said interrupt pin if at least a threshold number of assertions is reached during a window of time.

19. The system as recited in claim 18 wherein said threshold number of assertions is 20.

20. The system as recited in claim 15 wherein said AC input signals are at a control voltage and said square wave signals are at a digital logic voltage.

21. The system as recited in claim 15 wherein said multiplexer is configured to select among said square wave signals in a round-robin manner.