MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM

• US 20150331625A1
• Filed: 08/21/2014
• Published: 11/19/2015
• Est. Priority Date: 05/16/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aoyama, Norio, NISHIKUBO, Ryuji, Matsudaira, Hiroki
• Granted Patent: US 9,465,537 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks, and a controller controlling the nonvolatile memory. The controller cyclically executes patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks of the nonvolatile memory.

Claims

1. A memory system comprising:

a nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of word lines, each of the word lines including a plurality of memory cells, the plurality of memory cells having a storage capacity for one or more pages; and

a controller controlling the nonvolatile memory, wherein

the controller is configured to cyclically execute patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of the word lines in each of the blocks.

2. The memory system according to claim 1, wherein the controller is configured to cyclically execute patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to one of the word lines in each of the blocks.

3. The memory system according to claim 2, wherein the controller is configured to change a word line as an execution target of the patrol read each time the patrol read cycle is started.

4. The memory system according to claim 1, wherein the controller is configured to exclude, from targets of the patrol read, block to which data has been written after the patrol read is started.

5. The memory system according to claim 1, wherein the controller is configured to exclude, from targets of the patrol read, block having data that is to be moved to another block after the patrol read is started.

6. The memory system according to claim 1, wherein the controller is configured to execute the patrol read for one page with a low reliability among a plurality of pages connected to some of word lines in each of the blocks.

7. The memory system according to claim 1, wherein the patrol read is executed on blocks including valid data.

8. The memory system according to claim 1, wherein the patrol read includes error correction that is performed using an error-correcting code added to the data.

9. The memory system according to claim 8, wherein when number of errors in the read data exceeds a predetermined threshold, the controller moves data in a block including the read data to another block.

10. The memory system according to claim 1, wherein the nonvolatile memory is a NAND flash memory.

11. A method of controlling a memory system including a nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of word lines, each of the word lines including a plurality of memory cells, the plurality of memory cells having a storage capacity for one or more pages, the method comprising

cyclically executing patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks.

12. The method of controlling the memory system according to claim 11, wherein the patrol read is executed on pages connected to one of the word lines in each of the blocks.

13. The method of controlling the memory system according to claim 12, further comprising changing a word line as an execution target of the patrol read each time the patrol read cycle is started.

14. The method of controlling the memory system according to claim 11, further comprising excluding, from targets of the patrol read, block to which data has been written after the patrol read is started.

15. The method of controlling the memory system according to claim 11, further comprising excluding, from targets of the patrol read, block-having data that is to be moved to another block after the patrol read is started.

16. The method of controlling the memory system according to claim 11, further comprising executing the patrol read for one page with a low reliability among a plurality of pages connected to some of word lines in each of the blocks.

17. The method of controlling the memory system according to claim 11, wherein the patrol read is executed on blocks including valid data.

18. The method of controlling the memory system according to claim 11, wherein the-patrol read includes error correction that is performed using an error-correcting code added to the data.

19. The method of controlling the memory system according to claim 18, further comprising moving data in a block including the read data to another block when number of errors in the read data exceeds a predetermined threshold.

20. The method of controlling the memory system according to claim 11, wherein the nonvolatile memory is a NAND flash memory.