METHOD OF OPERATING SEMICONDUCTOR DEVICE

• US 20150332783A1
• Filed: 09/02/2014
• Published: 11/19/2015
• Est. Priority Date: 05/14/2014
• Status: Abandoned Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: JEONG, Yeon Joo
• Application Number:
  US14/475,187
• Publication Number:
  US 20150332783A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A method of operating a semiconductor device includes programming a first cell, verifying a second cell adjacent to the first cell, and repeating the programming of the first cell and the verifying of the second cell until the verifying of the second cell passes.

Claims

1. A method of operating a semiconductor device, the method comprising:

programming a first cell;

verifying a second cell adjacent to the first cell; and

repeating the programming of the first cell, and the verifying of the second cell until the verifying of the second cell passes,

wherein a threshold voltage of the second cell is increased by performing the programming the first cell.

2. The method of claim 1, wherein the programming of the first cell is performed by applying a program voltage to a first line coupled to the first cell.

3. The method of claim 1, wherein the verifying of the second cell is performed by applying a verify voltage to a second line coupled to the second cell.

4. The method of claim 3, wherein the verifying of the second cell is performed by applying a pass voltage to a first line coupled to the first cell.

5. The method of claim 1, wherein a program voltage for the programming of the first cell is gradually increased whenever the programming of the first cell and the verifying of the second cell are repeated.

6. A method of operating a semiconductor device including a memory block having a plurality of cell strings comprising dummy cells coupled between selection transistors and memory cells, the method comprising:

programming the dummy cells when an erase operation on the memory block is completed;

verifying the selection transistors; and

repeating the programming of the dummy cells, and the verifying of the selection transistors until the verifying of the selection transistors passes,

wherein a threshold voltage of the selection transistor is increased by performing the programming the dummy cells.

7. The method of claim 6, wherein the programming of the dummy cells is performed by applying a program voltage to dummy lines coupled to the dummy cells.

8. The method of claim 6, wherein the verifying of the selection transistors is performed by applying a verify voltage to selection lines coupled to the selection transistors.

9. The method of claim 8, wherein the verifying of the selection transistors is performed by applying a pass voltage to dummy lines coupled to the dummy cells, and word lines coupled to the memory cells.

10. The method of claim 6, further comprising comparing a number of times of the verifying of the selection transistors with a critical number.

11. The method of claim 10, wherein the critical number is set to a maximum number of times of the verifying of the selection transistors.

12. The method of claim 10, wherein a program operation of the dummy cells is determined as a fail when the number of times of the verifying of the selection transistors is greater than or equal to the critical number, or

the programming of the dummy cells and the verifying of the selection transistors are repeated until the verifying of the selection transistors passes when the number of times of the verifying of the selection transistors is less than the critical number.

13. The method of claim 6, wherein a program voltage for the programming of the first cell is gradually increased whenever the programming of the dummy cells and the verifying of the selection transistors are repeated.

14. A method of operating a semiconductor device including a memory block having a plurality of cell strings comprising dummy cells coupled between selection transistors and memory cells, the method comprising:

performing an erase operation on the memory block;

performing a program operation on the dummy cells to trap electrons of the dummy cells;

performing a verify operation on the selection transistors; and

repeating the performing the program operation on the dummy cells and the performing of the verify operation until the verify operation passes,

wherein a density of the electrons in a channel region adjacent to the selection transistors is reduced by performing the program operation on the dummy cells.

15. The method of claim 14, wherein the electrons in the channel region adjacent to the selection transistors are pushed away from the channel region by a repulsive force with the trapped electrons of the dummy cells.

16. The method of claim 15, wherein the programming of the dummy cells is performed by applying a program voltage to dummy lines coupled to the dummy cells.

17. The method of claim 16, wherein a program voltage for the program operation on the dummy cells gradually increased whenever the verify operation on the selection transistors is repeated.

18. The method of claim 14, wherein the verify operation is performed by applying a verify voltage to selection lines coupled to the selection transistors.

19. The method of claim 18, further comprising comparing a number of times of the verify operations with a critical number.

20. The method of claim 19, wherein the verify operation is determined as a fail when the number of times the verify operation greater than or equal to the critical number, or

the program operation and the verify operation on the selection transistors are repeated until the verify operation passes when the number of times of the verify operation is less than the critical number.