MULTIPLE DATA LINE MEMORY AND METHODS

• US 20150333001A1
• Filed: 07/27/2015
• Published: 11/19/2015
• Est. Priority Date: 10/26/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji, Feeley, Peter Sean, Goda, Akira
• Granted Patent: US 11,075,163 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.

Claims

1. An apparatus comprising:

a row of strings of charge storage devices, each string comprising a plurality of charge storage devices between a drain select gate transistor and a source select gate transistor; and

a plurality of data lines associated with the row of strings of charge storage devices, each data line associated with the row being coupled to a plurality of the strings in the respective row wherein adjacent strings within the row of strings of charge storage devices are coupled to different data lines.

2. The apparatus of claim 1, wherein the plurality of data lines associated with the row of strings of charge storage devices comprises four data lines.

3. The apparatus of claim 2, wherein each data line associated with the row is coupled to every fourth string of charge storage devices.

4. The apparatus of claim 1, wherein each charge storage device comprises a floating gate transistor.

5. The apparatus of claim 1, wherein each charge storage device comprises a charge trap transistor having single level charge storage or multilevel charge storage.

6. The apparatus of claim 1, wherein each drain select gate transistor forms a p-n junction with a respective pillar comprising a respective string of charge storage devices of the plurality of strings of charge storage devices.

7. The apparatus of claim 6, wherein each source select gate transistor forms a p-n junction with the respective pillar, the source select gate transistor coupled to a common source.

8. The apparatus of claim 6, wherein each p-n junction couples the respective pillar to its respective data line of the plurality of data lines.

9. The apparatus of claim 1, wherein each of the plurality of data lines is formed in a separate tier of a semiconductor construction of the row of strings of charge storage devices.

10. An apparatus comprising:

a respective plurality of data lines associated with each row of vertical strings of charge storage devices of a plurality of rows of vertical strings of charge storage devices in a block of charge storage devices, each data line associated with a respective row of vertical strings being coupled to a plurality of the vertical strings in the respective row of vertical strings, wherein adjacent vertical strings are coupled to different data lines and each vertical string comprises a plurality of charge storage devices between a drain select gate and a source select gate; and

a common source coupled to the source select gates of all of the vertical strings of the block.

11. The apparatus of claim 10, wherein the plurality of data lines comprise aluminum or copper.

12. The apparatus of claim 10, wherein each drain select gate forms a drain cap on each respective pillar of charge storage devices.

13. The apparatus of claim 12, wherein each source select gate forms a source cap on each respective pillar of charge storage devices.

14. The apparatus of claim 12, further comprising a metal plug formed on and in contact with the drain cap.

15. An apparatus comprising:

a plurality of tiers of data lines associated with a block of vertical strings of charge storage devices, the block comprising a plurality of rows of vertical strings of charge storage devices, each vertical string being coupled to a respective one of the data lines wherein adjacent vertical strings within each row of the plurality of rows and adjacent vertical strings of different rows of the plurality of rows are coupled to different data lines and each data line associated with a respective row coupled to a plurality of vertical strings within the respective row, each vertical string comprising a plurality of charge storage devices between a select gate drain and a select gate source; and

a common source coupled to the select gate source of all of the vertical strings of the block.

16. The apparatus of claim 15, wherein each vertical string of charge storage devices comprises:

a semiconductor pillar;

a first dielectric at least partially surrounding the semiconductor pillar;

a floating gate at least partially surrounding the first dielectric;

a second dielectric at least partially surrounding the floating gate; and

a control gate at least partially surrounding the second dielectric.

17. The apparatus of claim 16, wherein the control gate comprises a metal silicide control gate.

18. The apparatus of claim 17, wherein the metal silicide comprises one of CoSi, TiSi, WSi, NiSi, TaSi, MoSi, or PtSi.

19. The apparatus of claim 16, further comprising a third dielectric between the second dielectric and the control gate.

20. The apparatus of claim 15, wherein each of the plurality of vertical strings of charge storage devices is formed on a respective semiconductor pillar and the plurality of tiers of data lines are formed over the semiconductor pillars.