METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR CHIPS, AND OPTOELECTRONIC SEMICONDUCTOR CHIP

• US 20150333047A1
• Filed: 12/12/2013
• Published: 11/19/2015
• Est. Priority Date: 12/18/2012
• Status: Abandoned Application

• Current Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: PFEUFFER, Alexander F.
• Application Number:
  US14/653,839
• Publication Number:
  US 20150333047A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/385 the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

What is specified is a method for producing a plurality of optoelectronic semiconductor chips (1) each having a plurality of pixels (25). A semiconductor layer sequence (2) having an active region (20) provided for generating and/or detecting radiation, said active region being formed between a first semiconductor layer (21) a second semiconductor layer (22), is provided. The semiconductor layer sequence is fixed to a carrier (5) with a plurality of first connection areas (51), such that the first semiconductor layer is electrically conductively connected to the first connection areas. Isolating trenches (27) are formed in the semiconductor layer sequence fixed to the carrier, in order to form the pixels, wherein the isolating trenches extend through the semiconductor layer sequence. A contact layer (6) is formed, which electrically conductively connects the second semiconductor layer to a second connection area (52) of the carrier. The carrier is singulated into the plurality of semiconductor chips each having a plurality of pixels. Furthermore, an optoelectronic semiconductor chip (1) is specified.

Claims

1. A method for producing a plurality of optoelectronic semiconductor chips, each of which comprises a plurality of pixels, having the steps:

a) providing a semiconductor layer sequence having an active region intended to generate and/or detect radiation, which is formed between a first semiconductor layer and a second semiconductor layer;

b) providing a carrier having a plurality of first connection surfaces;

c) fastening the semiconductor layer sequence on the carrier, so that the first semiconductor layer is electrically conductively connected to the first connection surfaces;

d) forming separating trenches in the semiconductor layer sequence which is fastened on the carrier in order to form the pixels, the separating trenches extending through the semiconductor layer sequence;

e) forming a contact layer, which connects the second semiconductor layer electrically conductively to a second connection surface of the carrier; and

f) singulating the carrier into the plurality of semiconductor chips, each of which comprises a plurality of pixels.

2. The method according to claim 1,

wherein the semiconductor layer sequence is free of recesses in the region of the semiconductor chips in step c).

3. The method according to claim 1,

wherein alignment is carried out relative to alignment marks, which are formed on the carrier, during the formation of the separating trenches.

4. The method according to claim 1,

wherein the semiconductor layer sequence is provided with a metal interlayer before step c).

5. The method according to claim 4,

wherein the metal interlayer is cut through between step c) and step f).

6. The method according to claim 1, wherein

the semiconductor layer sequence is provided with a metal interlayer before step c);

alignment windows are formed in the metal interlayer before step c); and

the semiconductor layer sequence is positioned relative to the carrier in step c) so that alignment marks on the carrier overlap with the alignment windows.

7. The method according to claim 1, wherein the semiconductor layer sequence is deposited epitaxially on a growth substrate, and the growth substrate is removed before step d).

8. An optoelectronic semiconductor chip having a semiconductor layer sequence that comprises an active region intended to generate and/or receive radiation, which is arranged between a first semiconductor layer and a second semiconductor layer, wherein

the semiconductor layer sequence is subdivided into a plurality of pixels;

the semiconductor chip comprises a carrier, on which the semiconductor layer sequence is arranged and which comprises a driver circuit for the individual pixels;

the carrier comprises, for each pixel, a first connection surface which is electrically conductively connected to the first semiconductor layer of the pixels; and

the second semiconductor layer is connected electrically conductively to a second connection surface by a contact layer, the contact layer covering a radiation transmission surface facing away from the carrier at least in regions.

9. The semiconductor chip according to claim 8,

wherein the pixels of the semiconductor layer sequence taper at least in regions with an increasing distance from the carrier.

10. The semiconductor chip according to claim 8,

wherein the second semiconductor layer of each pixel is respectively connected electrically conductively by the contact layer to at least one second connection surface assigned to the pixel.

11. The semiconductor chip according to claim 8,

wherein the first connection surface extends around the at least one second connection surface.

12. The semiconductor chip according to claim 8, wherein the at least one second connection surface is arranged in an edge region or in a corner region of the first connection surface.

13. The semiconductor chip according to claim 8, wherein the first connection surface extends along at least two edges of the second connection surface.

14. The semiconductor chip according to claim 8, wherein each pixel comprises at least one cutout in the semiconductor layer sequence, and the contact layer extends from the second connection surface through the cutout to the second semiconductor layer.

15. The semiconductor chip according to claim 8,

wherein the second semiconductor layers of at least two neighboring pixels are electrically conductively connected to one another by the contact layer.

16. The semiconductor chip according to claim 8, wherein the pixels are separated from one another by separating trenches, and the contact layer extends in regions in the separating trenches.

17. The semiconductor chip according to claim 16,

wherein the contact layer comprises a metal layer, which extends in the form of a grid in the separating trenches.

18. The semiconductor chip according to claim 8, wherein the contact layer comprises a TCO material.

19. (canceled)

20. An optoelectronic semiconductor chip having a semiconductor layer sequence that comprises an active region intended to generate and/or receive radiation, which is arranged between a first semiconductor layer and a second semiconductor layer, wherein

the semiconductor layer sequence is subdivided into a plurality of pixels;

the semiconductor chip comprises a carrier, on which the semiconductor layer sequence is arranged and which comprises a driver circuit for the individual pixels;

the carrier comprises, for each pixel, a first connection surface which is electrically conductively connected to the first semiconductor layer of the pixels;

the second semiconductor layer is connected electrically conductively to a second connection surface by a contact layer, the contact layer covering a radiation transmission surface facing away from the carrier at least in regions; and

the first connection surface extends around the at least one second connection surface or along at least two edges of the second connection surface.