DUAL SILICIDE FORMATION METHOD TO EMBED SPLIT GATE FLASHMEMORY IN HIGH-K METAL GATE (HKMG) TECHNOLOGY

• US 20150333082A1
• Filed: 06/05/2014
• Published: 11/19/2015
• Est. Priority Date: 05/16/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Wu, Wei Cheng, Kao, Ya-Chen, Chu, Fang-Lan
• Granted Patent: US 9,276,010 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device.

Claims

1. An integrated circuit (IC) comprising:

a semiconductor substrate including a periphery region and a memory cell region;

a high-k metal gate (HKMG) gate electrode disposed on the periphery region;

a first memory cell disposed on the memory cell region, comprising a select gate (SG) and a memory gate (MG);

a silicide layer disposed on a SG top surface or a MG top surface of the first memory cell;

a hard mask layer in contact with an upper surface of the HKMG gate electrode; and

metal contacts extending into the silicide layer on the SG top surface or the MG top surface.

2. The IC of claim 1, wherein a second memory cell, which is a mirror image of the first memory cell is disposed adjacent to the first memory cell.

3. The IC of claim 1, wherein:

the silicide layer is disposed on top surfaces of both the MG and the SG of the first memory cell.

4. The IC of claim 3, wherein the first memory cell further comprises:

a charge-trapping layer arranged between neighboring sidewalls of the MG and the SG, the charge trapping layer extending under the MG; and

a sidewall spacer abutting an outer side wall of the MG.

5. The IC of claim 4, further comprising:

a base dielectric layer disposed above a base surface of the semiconductor substrate below the SG and the charge-trapping layer;

a base silicide layer disposed over a base surface of the semiconductor substrate on active regions of the semiconductor substrate; and

a CESL (contact etch stop layer) disposed above the base silicide layer in the active regions.

6. The IC of claim 4, wherein:

the silicide layer is disposed partially, but not entirely, on the SG top surfaces and the MG top surface of the first memory cell; and

the hard mask layer is disposed over a top surface of the charge-trapping layer.

7. The IC of claim 4, wherein:

the silicide layer is disposed on the SG top surface of the first memory cell; and

the hard mask layer is disposed over top surfaces of the HKMG gate electrode, the charge trapping layer, the MG, and the sidewall spacer.

8. The IC of claim 5, wherein:

the silicide layer is disposed on the MG top surface of the first memory cell; and

the hard mask layer is disposed over top surfaces of the HKMG gate electrode, the SG, the charge trapping layer, sidewall spacer and the CESL layer.

9. The IC of claim 5, wherein:

the MG and the SG comprise polysilicon;

the semiconductor substrate comprises Si;

the silicide layer comprises NiSi (nickel silicide);

the CESL comprises SiN (silicon nitride); and

the hard mask-layer comprises SiO2 (silicon oxide), SiN or SION.

21. The IC of claim 1, wherein the hard mask layer abuts a portion of the SG top surface not covered by the silicide layer or a portion of the MG top surface not covered by the silicide layer.

10. An integrated circuit (IC) comprising:

a semiconductor substrate including a periphery region and a memory cell region;

a HKMG (high-k metal gate) circuit disposed on the periphery region;

two neighboring split gate flash memory cells arranged on the memory cell region, each memory cell including a select gate (SG) and a memory gate (MG), wherein top surfaces of the HKMG circuit and the split gate flash memory cells are co-planar;

a silicide layer disposed on a SG top surface or a MG top surface of both split gate flash memory cells;

a hard mask layer disposed over upper surfaces of gate electrodes within the HKMG circuit; and

a CESL (contact etch stop layer) disposed between the semiconductor substrate the hard mask layer; and

a metal contact vertically extending to the HKMG gate electrode through the hard mask layer and a dielectric layer overlying the hard mask layer.

11. The IC of claim 10, wherein the hard mask layer is disposed on a portion of the SG top surface not covered by the silicide layer or on a portion of the MG top surface not covered by the silicide layer.

13. The IC of claim 11, wherein the hard mask layer is further disposed partially, but not entirely, over top surfaces of a charge-trapping layer and the SG of each memory cell.

14. The IC of claim 11, wherein the HKMG circuit comprises a HV (high voltage) HKMG transistor and a HKMG periphery circuit.

15. The IC of claim 14, wherein the HKMG circuit comprises a static random access memory (SRAM) cell, an input/output cell or a core cell.

16. The IC of claim 11, further comprising:

an ILD (inter-layer dielectric) layer disposed above top surfaces of the split gate flash memory cells and the HKMG circuit;

metal contacts extending to active regions on the substrate and to top surfaces of the MG and SG, wherein metal contacts perforate through the ILD layer and the hard mask layer; and

a protective barrier layer disposed above the metal contacts and the ILD layer.

12. (canceled)

17. A method of forming an integrated circuit (IC) comprising:

forming a pair of memory cells over a first region on a semiconductor substrate, each memory cell comprising a select gate (SG) and a memory gate (MG);

forming a high-k metal gate (HKMG) circuit over a second region on the semiconductor substrate;

performing chemical mechanical polishing (CMP) to make top surfaces of the memory cells and the HKMG circuit co-planar;

forming a hard mask layer over the top surfaces of the memory cells and the HKMG circuit;

selectively removing the hard mask layer to expose top surfaces of the SG or MG of the memory cells partially or completely;

forming a self-aligned silicide (salicide) layer over the exposed top surfaces of the memory cells;

forming a first inter-layer dielectric (ILD) layer over top surfaces of the pair of memory cells and the HKMG circuit; and

forming metal contacts extending to the silicide layer.

18. The method of claim 17, wherein forming a pair of memory cells comprises:

forming a sacrificial spacer over a semiconductor substrate;

forming a select gate (SG) material layer over a top surface and sidewalls of the sacrificial spacer;

performing a first etch back process on the SG material layer to expose the top surface of the sacrificial spacer and upper sidewall regions of the sacrificial spacer and thereby forming a first and second SG structures;

forming a conformal silicide-blocking layer that extends over the first and second SG structures and over the top surface of the sacrificial spacer;

performing a second etch back process to remove the conformal silicide-blocking layer from over the top surface of the sacrificial spacer while leaving a portion on the first and second SG structures and thereby forming first and second silicide-blocking caps;

forming a conformal charge-trapping layer extending over the top surface of the sacrificial spacer and over the first and second silicide-blocking caps;

forming a conformal memory gate (MG) material layer over the charge-trapping layer;

forming a conformal dielectric spacer layer over the conformal MG material layer; and

performing a third etch back procedure to remove portions of the conformal charge-trapping layer, portions of the conformal MG material layer, and portions of the conformal spacer dielectric layer, to thereby form first and second self-aligned MG structures on outermost sidewalls of the first and second SG structures, respectively.

19. The method of claim 18, further comprising:

forming source/drain regions in the semiconductor substrate;

removing the sacrificial spacer to form a recess between inner sidewalls of the first and second SG structures;

forming a silicide layer on the semiconductor substrate in the recess and over the source/drain regions;

forming a conformal contact etch-stop layer (CESL) on the semiconductor substrate in the recess and over the SG and MG structures;

forming a second ILD layer extending over the CESL and extending downwardly into the recess; and

performing a chemical mechanical polishing (CMP) operation on the first ILD layer.

20. The method of claim 19, further comprising:

depositing a protective barrier layer over the first ILD layer and over top surfaces of the metal contacts.